{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T23:37:18Z","timestamp":1725493038685},"publisher-location":"Berlin, Heidelberg","reference-count":65,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540678991"},{"type":"electronic","value":"9783540446149"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2000]]},"DOI":"10.1007\/3-540-44614-1_63","type":"book-chapter","created":{"date-parts":[[2007,10,20]],"date-time":"2007-10-20T13:25:22Z","timestamp":1192886722000},"page":"585-594","source":"Crossref","is-referenced-by-count":0,"title":["Reconfigurable Systems: New Activities in Asia"],"prefix":"10.1007","author":[{"given":"Hideharu","family":"Amano","sequence":"first","affiliation":[]},{"given":"Yuichiro","family":"Shibata","sequence":"additional","affiliation":[]},{"given":"Masaki","family":"Uno","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2002,4,12]]},"reference":[{"key":"63_CR1","doi-asserted-by":"crossref","unstructured":"H. Amano, Y. Shibata, \u201cReconfigurable Systems: Activities in Asia and South Pacific,\u201d Proc. of ASP-DAC, pp. 453\u2013457, 1998.","DOI":"10.1109\/ASPDAC.1998.669521"},{"key":"63_CR2","unstructured":"K. Nakajima, H. Mori, H. Sato, T. Takahashi, H. Asami, Y. Mizukami, M. Iida, K. Shindome, \u201cFPGA-based Parallel Machine RASH,\u201d Proc. of JSPP\u201999, pp. 222. (in Japanese)"},{"key":"63_CR3","unstructured":"H. Asami, M. Iida, K. Nakajima, H. Mori, \u201cImprovement of DES circuit on FPGAbased Parallel Machine RASH,\u201d Tech. Rep. of IEICE. CPSY99-111. (in Japanese)"},{"key":"63_CR4","doi-asserted-by":"crossref","unstructured":"N. Suganuma, Y. Murata, S. Nakata, S. Nagata, M. Tomita, K. Hirano, \u201cReconfigurable Machine and Its Application to Logic Diagnosis,\u201d ICCAD-92, pp. 373\u2013376, 1992.","DOI":"10.1109\/ICCAD.1992.279344"},{"issue":"10","key":"63_CR5","first-page":"1705","volume":"E76-A","author":"M. Tomita","year":"1993","unstructured":"M. Tomita, N. Suganuma, K. Hirano, \u201cReconfigurable Machine and Its Application to Logic Simulation,\u201d IEICE Trans. Fundamentals, Vol. E76-A, No. 10, pp. 1705\u20131712, 1993.","journal-title":"IEICE Trans. Fundamentals"},{"key":"63_CR6","unstructured":"M. Numa, \u201cReconfigurable Machines: RM-I to RM-IV and Their Applications,\u201d IEICE Technical Report CPSY96-92, 1996 (in Japanese)"},{"key":"63_CR7","doi-asserted-by":"crossref","unstructured":"B. Gungher, G. Milne, L. Narasimhan, \u201cAssessing Document Relevance with Run-Time Reconfigurable Machines,\u201d Proc. of the IEEE Symposium on FPGAs for Custom Computing Machines, pp. 10\u201317, 1996.","DOI":"10.1109\/FPGA.1996.564737"},{"key":"63_CR8","unstructured":"X.-P. Ling, Y. Shibata, H. Miyazaki, H. Amano, \u201cTotal System Image of the Reconfigurable Machine WASMII,\u201d Proc. of International conference on Parallel Distributed Processing Techniques and Applications, pp. 1092\u20131096, 1997."},{"key":"63_CR9","doi-asserted-by":"crossref","unstructured":"X.-P. Ling, H. Amano, \u201cWASMII: a Data Driven Computer on a Virtual Hardware,\u201d Proc. of the IEEE Symposium on FPGAs for Custom Computing Machines, pp. 33\u201342, 1993.","DOI":"10.1109\/FPGA.1993.279481"},{"issue":"3","key":"63_CR10","doi-asserted-by":"publisher","first-page":"253","DOI":"10.1007\/BF01212871","volume":"9","author":"X.-P. Ling","year":"1995","unstructured":"X.-P. Ling, H. Amano, \u201cWASMII: an MPLD with Data-Driven Control on a Virtual Hardware,\u201d Journal of Supercomputing, Kluwer Academic Publishers, Vol. 9, No. 3, pp. 253\u2013276, 1995.","journal-title":"Journal of Supercomputing"},{"key":"63_CR11","doi-asserted-by":"crossref","unstructured":"O. Yamamoto, Y. Shibata, H. Kurokawa, H. Amano, \u201cA Reconfigurable Markov Chain Simulator for Analysis of Parallel Systems,\u201d Proc. of IEEE the Innovated System in Silicon, 1997.","DOI":"10.1109\/ICISS.1997.630251"},{"key":"63_CR12","unstructured":"H. Miyazaki, Y. Shibata, A. Takayama, X-P. Ling, H. Aamano, \u201cEmulation of Multichip WASMII on Reconfigurable System Testbed FLEMING,\u201d Proc. of PACT98 workshop on reconfigurable computing, pp. 47\u201352, 1998."},{"key":"63_CR13","doi-asserted-by":"crossref","unstructured":"T. Yamauchi, S. Nakaya, N. Kajihara, \u201cSOP: A Reconfigurable Massively Parallel System and Its Control-Data-Flow based Compiling Method\u201d Proc. of the IEEE Symposium on FPGAs for Custom Computing Machines, pp. 148\u2013156, 1996.","DOI":"10.1109\/FPGA.1996.564793"},{"key":"63_CR14","unstructured":"H. Sasaki, H. Maruyama, H. Tsukioka, S. Shoji, H. Kobayashi, T. Nakamura, \u201cAn Architecture of the Reconfigurable Synchronous Dataflow Computer and its Software Development Environment,\u201d Proc. of the 7th FPGA\/PLD Design conference and exhibit., pp. 9\u201314, 1999. (in Japanese)"},{"key":"63_CR15","unstructured":"S. Ichikawa, T. Shimada, \u201cDesign and Implementation of Reconfigurable PCI Card,\u201d IEICE Technical Report, CPSY96-97, 1996 (in Japanese)"},{"key":"63_CR16","doi-asserted-by":"crossref","unstructured":"S. Ichikawa, L. Udorn, K. Konishi, \u201cHardware Accelerator for Subgraph Isomorphism Problems,\u201d Proc. of FCCM 2000.","DOI":"10.1109\/FPGA.2000.903417"},{"key":"63_CR17","unstructured":"M. Satachi, A. Kanomata, \u201cMicrocomputer-FPGA Cooperation Board Camereon,\u201d Proc. of the 5th Japanese FPGA\/PLD Conference and Exhibit, pp. 259\u2013267, 1997 (in Japanese)"},{"key":"63_CR18","unstructured":"Y. Noguchi, K. Saisho, A. Fukuda, \u201cA Reconfigurable Simualtion System with Programmable Devices,\u201d IPSJ Tech. Rep. 98-ARC-131, 1998 (in Japanese)"},{"key":"63_CR19","doi-asserted-by":"crossref","unstructured":"A. Tsutsui, T. Miyazaki, \u201cYARDS: FPGA\/MPU Hybrid Architecture for Telecommunication Data Processing,\u201d Proc. of the ACM\/SIGDA International Symposium on Field Programmable Gate Arrays, pp. 93\u201399, 1997.","DOI":"10.1145\/258305.258317"},{"key":"63_CR20","series-title":"Lect Notes Comput Sci","doi-asserted-by":"crossref","first-page":"366","DOI":"10.1007\/BFb0055264","volume-title":"Proc. of the International Workshop on Field-Programmable Logic and Applications","author":"T. Miyazaki","year":"1998","unstructured":"T. Miyazaki, K. Shirakawa, M. Katayama, T. Murooka, A. Takahara, \u201cA Transmutable Telecom System,\u201d Proc. of the International Workshop on Field-Programmable Logic and Applications, (LNCS 1482), pp. 366\u2013375, 1998."},{"key":"63_CR21","series-title":"Lect Notes Comput Sci","doi-asserted-by":"crossref","first-page":"421","DOI":"10.1007\/BFb0055273","volume-title":"Proc. of the International Workshop on Field-Programmable Logic and Applications","author":"S. Yamagiwa","year":"1998","unstructured":"S. Yamagiwa, M. Ono, T. Yamazaki, P. Kulkasem, M. Hirota, K. Wada, \u201cMaestro-Link: A High Performance Interconnect for PC Cluster,\u201d Proc. of the International Workshop on Field-Programmable Logic and Applications, (LNCS 1482), pp. 421\u2013425, 1998."},{"key":"63_CR22","doi-asserted-by":"crossref","unstructured":"H. Nishi, K. Tasho, T. Kuhoh, J. Yamamoto, H. Amano, \u201cA Local area system network RHiNET-1: a network for high performance parallel computing,\u201d Proc. of IEEE High Performance Distributed Computing 2000.","DOI":"10.1109\/HPDC.2000.868665"},{"key":"63_CR23","doi-asserted-by":"crossref","unstructured":"T. McDermott, P. Ryan, M. Shand, D. Skellern, T. Percival, N. Weste, \u201cA Wireless LAN Demodulator in a Pamette: Design and Experience,\u201d Proc. of the IEEE Symposium on FPGAs for Custom Computing Machines, pp. 40\u201345, 1997.","DOI":"10.1109\/FPGA.1997.624603"},{"key":"63_CR24","doi-asserted-by":"crossref","unstructured":"M. Cummings, S. Haruyama, \u201cFPGA in the Software Radio,\u201d IEEE Communications Magazine, Feb. pp. 108\u2013112, 1999.","DOI":"10.1109\/35.747258"},{"key":"63_CR25","unstructured":"T. Yamaguchi, Y. Hashiyama, S. Okuma, \u201cA Study on Reconfigurable Computing System for Encryption,\u201d IEICE Tech. Rep. CPSY99-82. (in Japanese)"},{"key":"63_CR26","unstructured":"H. Nakano, \u201cFlexible Image Processor Board XE\/55V,\u201d Proc. of the 2nd Japanese FPGA\/PLD Conference and Exhibit, pp. 365\u2013371, 1994 (in Japanese)"},{"key":"63_CR27","series-title":"Lect Notes Comput Sci","doi-asserted-by":"crossref","first-page":"410","DOI":"10.1007\/3-540-63465-7_246","volume-title":"Proc. of the International Workshop on Field-Programmable Logic and Applications","author":"C. C. Jong","year":"1997","unstructured":"C. C. Jong, Y. Y. H. Lam, L. S. Ng, \u201cFPGAs Implementation of a Digital IQ Demodulator,\u201d Proc. of the International Workshop on Field-Programmable Logic and Applications, (LNCS 1304), pp. 410\u2013417, 1997."},{"key":"63_CR28","unstructured":"H. Hikawa, K. Sato, H. Iwabuchi, \u201cReconfigurable Array-Processor Based on FPGA,\u201d Proc. of the 3rd Japanese FPGA\/PLD Conference and Exhibit, pp. 493\u2013504, 1995 (in Japanese)"},{"key":"63_CR29","unstructured":"Z-h. Liu, Y-q. Han, \u201cImplementation of FFT in FPGA Technology,\u201d Proc. of IEEE ASICON98, pp. 28\u201331, 1998."},{"key":"63_CR30","doi-asserted-by":"crossref","unstructured":"C. H. Dick, \u201cComputing the Discrete Fourier Transform on FPGA Based Systolic Arrays,\u201d Proc. of the ACM\/SIGDA International Symposium on Field Programmable Gate Arrays, pp. 129\u2013135, 1996.","DOI":"10.1109\/FPGA.1996.242440"},{"key":"63_CR31","series-title":"Lect Notes Comput Sci","doi-asserted-by":"crossref","first-page":"96","DOI":"10.1007\/3-540-61730-2_10","volume-title":"Proc. of the International Workshop on Field-Programmable Logic and Applications","author":"C. H. Dick","year":"1996","unstructured":"C. H. Dick, \u201cComputing 2-D DFTs Using FPGAs,\u201d Proc. of the International Workshop on Field-Programmable Logic and Applications, (LNCS 1142), pp. 96\u2013105, 1996."},{"key":"63_CR32","doi-asserted-by":"crossref","unstructured":"N. W. Bergmann, Y. Y. Chung, B. K. Gunther, \u201cEfficient Implementation of the DCT on Custom Computers,\u201d Proc. of the IEEE Symposium on FPGAs for Custom Computing Machines, pp. 244\u2013245, 1997.","DOI":"10.1109\/FPGA.1997.624628"},{"key":"63_CR33","unstructured":"A. Oue, T. Isshik, H. Kunieda, \u201cMPEG Video Encoder Based on Run-Time Reconfigurable Architecture,\u201d Proc. of IEEE ASICON98, pp. 83\u201391, 1998."},{"key":"63_CR34","unstructured":"M. Sekiyama, M. Nomura, K. Hiraki, \u201cValidity of Run-time Reconfigure at Treatment of Animation with Hardware,\u201d IPSJ Tech. Rep. 98-ARC-130-23, 1998. (in Japanese)"},{"key":"63_CR35","unstructured":"X-y. Meng, J. Liang, \u201cThe New Application of Built-in RAM of FPGA in Marine Navigation System,\u201d Proc. of IEEE ASICON98, pp. 8\u201311, 1998."},{"key":"63_CR36","series-title":"Lect Notes Comput Sci","doi-asserted-by":"crossref","first-page":"356","DOI":"10.1007\/BFb0055263","volume-title":"Proc. of the International Workshop on Field-Programmable Logic and Applications","author":"T. Maruyama","year":"1998","unstructured":"T. Maruyama, T. Funatsu, T. Hoshino, \u201cField-Programming Gate-Array System for Evolutionary Computation,\u201d Proc. of the International Workshop on Field-Programmable Logic and Applications, (LNCS 1482), pp. 356\u2013365, 1998."},{"key":"63_CR37","series-title":"Lect Notes Comput Sci","doi-asserted-by":"crossref","first-page":"491","DOI":"10.1007\/3-540-63465-7_255","volume-title":"Proc. of the International Workshop on Field-Programmable Logic and Applications","author":"K. Nukata","year":"1997","unstructured":"K. Nukata, Y. Shibata, H. Amano, Y. Anzai, \u201cA Reconfigurable Sensor-Data Processing system for Personal Robots,\u201d Proc. of the International Workshop on Field-Programmable Logic and Applications, (LNCS 1304), pp. 491\u2013500, 1997."},{"key":"63_CR38","unstructured":"Y. Ohsima, T. Matsumoto, K. Hiraki, \u201cReconfigurable GA Engine,\u201d Proc. of the 3rd Japanese FPGA\/PLD Conference and Exhibit, pp. 541\u2013548, 1995 (in Japanese)"},{"key":"63_CR39","unstructured":"M. Sano, Y. Takahashi, \u201cSIMD GA Machine Based on FPGA,\u201d Proc. of the 5th Japanese FPGA\/PLD Conference and Exhibit, pp. 241\u2013248, 1997 (in Japanese)"},{"key":"63_CR40","unstructured":"Y. Kitamura, M. Sasaki, T. Kanokogi, \u201cNeuro Processor Implementation Based on FPGA,\u201d Proc. of the 3rd Japanese FPGA\/PLD Conference and Exhibit, pp. 531\u2013539, 1995 (in Japanese)"},{"key":"63_CR41","unstructured":"K. Bando, Y. Iguchi, T. Yamada, \u201cDesign of a Device Simulation Engine Based on FPGA,\u201d Proc. of the 3rd Japanese FPGA\/PLD Conference and Exhibit, pp. 563\u2013567, 1995 (in Japanese)"},{"key":"63_CR42","unstructured":"C.K Chung and P.H.W. Leong, \u201cAn Architecture for solving boolean satisfiaability using runtime configurable hardware,\u201d Proc. of ICPP Workshop, pp. 346\u2013351, 1999."},{"issue":"4","key":"63_CR43","first-page":"415","volume":"14","author":"T. Yoshinaga","year":"1991","unstructured":"T. Yoshinaga, T. Baba, \u201cA Local Operating System for the A-NET Parallel Object Oriented Computer,\u201d Journal of Information Processing, Vol. 14, No. 4, pp. 415\u2013422, 1991.","journal-title":"Journal of Information Processing"},{"key":"63_CR44","series-title":"Lect Notes Comput Sci","doi-asserted-by":"crossref","first-page":"200","DOI":"10.1007\/3-540-61730-2_21","volume-title":"Proc. of the International Workshop on Field-Programmable Logic and Applications","author":"K. Inoue","year":"1996","unstructured":"K. Inoue, T. Kisuki, M. Okuno, E. Shimizu, T. Terasawa, H. Amano, \u201cATTEMPT-1: A Reconfigurable Multiprocessor Testbed,\u201d Proc. of the International Workshop on Field-Programmable Logic and Applications, (LNCS 1142), pp. 200\u2013209, 1996."},{"key":"63_CR45","unstructured":"S. Mitsugi, Y. Sawayama, \u201cMi-con builder: Design Support System for Development of Microcomputers,\u201d Proc. of the Altera PLD World 96, pp. 87\u201392, 1996 (in Japanese)"},{"key":"63_CR46","unstructured":"W. Ogata, \u201cReconfigurable Computer Architecture Evaluation System Based on FLEX8000,\u201d Proc. of Altera PLD World 96, pp. 101\u2013114, 1996 (in Japanese)"},{"key":"63_CR47","series-title":"Lect Notes Comput Sci","doi-asserted-by":"crossref","first-page":"280","DOI":"10.1007\/3-540-61730-2_30","volume-title":"Proc. of the International Workshop on Field-Programmable Logic and Applications","author":"Z. Salcic","year":"1996","unstructured":"Z. Salcic, B. Maunder, \u201cCCSimP \u2014 An Instruction-Level Custom-Configurable Processor for FPLDs,\u201d Proc. of the International Workshop on Field-Programmable Logic and Applications, (LNCS 1142), pp. 280\u2013289, 1996."},{"key":"63_CR48","series-title":"Lect Notes Comput Sci","first-page":"451","volume-title":"Proc. of the International Workshop on Field-Programmable Logic and Applications","author":"T. Maruyama","year":"1999","unstructured":"T. Maruyama, M. Takagi, T. Hoshino, \u201cHardware Implementation Techniques for Recursive Calls and Loops,\u201d Proc. of the International Workshop on Field-Programmable Logic and Applications, (LNCS 1673), pp. 451\u2013461, 1999."},{"key":"63_CR49","unstructured":"T. Nakano, A. Utama, M. Itabashi, A. Shiomi, M. Imai, \u201cThe Evaluation of Silicon TRON Design,\u201d IEICE Technical Report, CPSY93-62, 1993 (in Japanese)"},{"key":"63_CR50","doi-asserted-by":"crossref","unstructured":"T. Fujii, K. Furuta, M. Motomura, M. Nomura, M. Mizuno, K. Anjo, K. Wakabayashi, Y. Hirota, Y. Nakazawa, H. Ito, M. Yamashina, \u201cA Dynamically Reconfigurable Logic Engine with a Multi-Context Multi-Mode Unified-Cell Architecture,\u201d Proc. Intl. Solid-State Circuits Conf., pp. 360\u2013361 (1999).","DOI":"10.1109\/ISSCC.1999.759297"},{"key":"63_CR51","unstructured":"M. Yamashina, M. Motomura, \u201cReconfigurable Computing: Its concept and practical embodiment using newly developed DRL LSI,\u201d Proc. ASP-DAC 2000, pp. 329\u2013332, (2000)."},{"key":"63_CR52","unstructured":"M. Uno, Y. Shibata, H. Amano, K. Furuta, T. Fujii, M. Motomorura, \u201cA Virtual Hardware System on a DRL device,\u201d IEICE Tech. Rep. CPSY99-113, 2000. (in Japanese)"},{"key":"63_CR53","doi-asserted-by":"crossref","unstructured":"M. Motomura, Y. Aimoto, A. Shibayama, Y. Yabe, M. Yamashina, \u201c\u2019An Embedded DRAM-FPGA Chip with Instantaneous Logic Reconfiguration,\u201d Proc. Intl. Conf. on VLSI Circuits, pp. 55\u201356 (1997).","DOI":"10.1109\/VLSIC.1997.623804"},{"key":"63_CR54","doi-asserted-by":"crossref","unstructured":"K. Nagami, K. Oguri, T. Shiozawa, H. Ito, R. Konishi, \u201cPlastic Cell Architecture: Towards Reconfigurable Computating for General Purpose,\u201d in Proc. of FCCM\u201998, pp. 68\u201377, 1998.","DOI":"10.1109\/FPGA.1998.707883"},{"key":"63_CR55","series-title":"Lect Notes Comput Sci","doi-asserted-by":"crossref","first-page":"679","DOI":"10.1007\/BFb0097953","volume-title":"Proc. of IPPS\/SPDP99","author":"H. Nakada","year":"1999","unstructured":"H. Nakada, K. Oguri, N. Imlig, M. Inamori, R. Konishi, H. Ito, K. Nagami, T. Shiozawa, \u201cPlastic Cell Architecture: A Dynamically Reconfigurable Hardware-based Computer,\u201d in Proc. of IPPS\/SPDP99 LNCS1586, pp. 679\u2013687, 1999."},{"key":"63_CR56","unstructured":"Y. Kawano, H. Ochi, T. Tuda, \u201cDesign of FPAccA model 2.0 Chip \u2014 Reconfigurable Floating-Point-Unit Array-,\u201d IEICE Tech. Rep. CPSY99-112, 2000. (in Japanese)"},{"key":"63_CR57","unstructured":"N. Kajihara, S. Nakaya, T. Yamauchi, T. Inuo, \u201cThe Design and Implementation of an ALU Based Reconfigurable Adaptive Device,\u201d Proc. of 2000 RWC Symposium (TR-99-002), pp. 237\u2013242, 2000."},{"key":"63_CR58","series-title":"Lect Notes Comput Sci","doi-asserted-by":"crossref","first-page":"514","DOI":"10.1007\/978-3-540-48302-1_62","volume-title":"Proc. of the International Workshop on Field-Programmable Logic and Applications","author":"T. Maruyama","year":"1999","unstructured":"T. Maruyama, T. Hoshino, \u201cA Reconfigurable Architecture for High Speed Computation by Pipeline Processing,\u201d Proc. of the International Workshop on Field-Programmable Logic and Applications, (LNCS 1673), pp. 514\u2013519, 1999."},{"key":"63_CR59","unstructured":"Z-h. Huang, J-r. Tong, \u201cAn Efficient FPGA Logic Block for Word-oriented Data-path,\u201d Proc. of IEEE ASICON98, pp. 20\u201323, 1998."},{"key":"63_CR60","series-title":"Lect Notes Comput Sci","doi-asserted-by":"crossref","first-page":"347","DOI":"10.1007\/978-3-540-48302-1_36","volume-title":"Proc. of the International Workshop on Field-Programmable Logic and Applications","author":"M. Wojko","year":"1999","unstructured":"M. Wojko, \u201cPipelined Multipliers and FPGA Architectures,\u201d Proc. of the International Workshop on Field-Programmable Logic and Applications, (LNCS 1673), pp. 347\u2013352, 1999."},{"key":"63_CR61","unstructured":"S. Mitsugi, \u201cRotary Computer and Virtual Circuit,\u201d Proc. of the IPSJ 44th Annual Convention, 6\u2013109, 1992."},{"key":"63_CR62","unstructured":"S. Yoshimi (Fujitsu Inc.), \u201cMulti-function Programmable Logic device,\u201d Japan Patent (A), Hei2-130023, 1990."},{"key":"63_CR63","unstructured":"T. Sueyoshi, \u201cPresent Status and Problems of the Reconfigurable Computing Systems \u2014 Toward the Computer Evolution \u2014 \u201d IEICE Technical Report, CPSY96-91, 1996 (in Japanese)"},{"key":"63_CR64","unstructured":"Y. Shibata, H. Miyazaki, X.-P. Ling, H. Amano, \u201cHOSMII: a Virtual Hardware System Based on an FPGA Embedded with DRAM,\u201d IEICE Technical Report, CPSY97-45, 1997 (in Japanese)"},{"key":"63_CR65","unstructured":"M. Iida, M. Kuga, T. Sueyoshi, \u201cOn Chip Multi-processor Using Multithread Control Library Implemented as Hardware,\u201d Proc. on Joint Symposium on Parallel Processing, pp. 337\u2013344, 1997 (in Japanese)"}],"container-title":["Lecture Notes in Computer Science","Field-Programmable Logic and Applications: The Roadmap to Reconfigurable Computing"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/3-540-44614-1_63","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,5,3]],"date-time":"2019-05-03T18:06:26Z","timestamp":1556906786000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/3-540-44614-1_63"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2000]]},"ISBN":["9783540678991","9783540446149"],"references-count":65,"URL":"https:\/\/doi.org\/10.1007\/3-540-44614-1_63","relation":{},"ISSN":["0302-9743"],"issn-type":[{"type":"print","value":"0302-9743"}],"subject":[],"published":{"date-parts":[[2000]]}}}