{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,19]],"date-time":"2025-03-19T10:37:52Z","timestamp":1742380672979},"publisher-location":"Berlin, Heidelberg","reference-count":31,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540678991"},{"type":"electronic","value":"9783540446149"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2000]]},"DOI":"10.1007\/3-540-44614-1_66","type":"book-chapter","created":{"date-parts":[[2007,10,20]],"date-time":"2007-10-20T17:25:22Z","timestamp":1192901122000},"page":"615-625","source":"Crossref","is-referenced-by-count":6,"title":["Memory Access Schemes for Configurable Processors"],"prefix":"10.1007","author":[{"given":"Holger","family":"Lange","sequence":"first","affiliation":[]},{"given":"Andreas","family":"Koch","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2002,4,12]]},"reference":[{"key":"66_CR1","unstructured":"Amerson, R., \u201cTeramac \u2014 Configurable Custom Computing\u201d, Proc. IEEE Symp. on FCCMs, Napa 1995"},{"key":"66_CR2","doi-asserted-by":"crossref","unstructured":"Bertin, P., Roncin, D., Vuillemin, J., \u201cProgrammable Active Memories: A Performance Assessment\u201d, Proc. Symp. Research on Integrated Systems, Cambridge (Mass.) 1993","DOI":"10.1007\/3-540-56731-3_12"},{"key":"66_CR3","unstructured":"Box, B., \u201cField-Programmable Gate Array-based Reconfigurable Preprocessor\u201d, Proc. IEEE Symp. on FCCMs, Napa 1994"},{"key":"66_CR4","unstructured":"Buell, D., Arnold, J., Kleinfelder, W., \u201cSplash 2 \u2014 FPGAs in Custom Computing Machines\u201d, IEEE Press, 1996"},{"key":"66_CR5","unstructured":"Rupp, C., Landguth, M., Garverick, et al., \u201cThe NAPA Adaptive Processing Architecture\u201d, Proc. IEEE Symp. on FCCMs, Napa 1998"},{"key":"66_CR6","doi-asserted-by":"crossref","unstructured":"Hauser, J., Wawrzynek, J., \u201cGarp: A MIPS Processor with a Reconfigurable Coprocessor\u201d, Proc. IEEE Symp. on FCCMs, Napa 1997","DOI":"10.1109\/FPGA.1997.624600"},{"key":"66_CR7","doi-asserted-by":"crossref","unstructured":"Wittig, R., Chow, P., \u201cOneChip: An FPGA Processor with Reconfigurable Logic\u201d, Proc. IEEE Symp. on FCCMs, Napa 1996","DOI":"10.1109\/FPGA.1996.564773"},{"key":"66_CR8","doi-asserted-by":"crossref","unstructured":"Jacob, J., Chow, P., \u201cMemory Interfacing and Instruction Specification for Reconfigurable Processors\u201d, Proc. ACM Intl. Symp. on FPGAs, Monterey 1999","DOI":"10.1145\/296399.296446"},{"key":"66_CR9","unstructured":"Triscend, \u201cTriscend E5 CSoC Family\u201d, http:\/\/www.triscend.com\/products\/IndexE5.html , 2000"},{"key":"66_CR10","unstructured":"Altera, \u201cExcalibur Embedded Processor Solutions\u201d, http:\/\/www.altera.com\/html\/products\/excalibur.html , 2000"},{"key":"66_CR11","unstructured":"TSI-Telsys, \u201cACE2card User\u2019s Manual\u201d, hardware documentation, 1998"},{"key":"66_CR12","unstructured":"Koch, A., \u201cA Comprehensive Platform for Hardware-Software Co-Design\u201d, Proc. Intl. Workshop on Rapid-Systems Prototyping, Paris 2000"},{"key":"66_CR13","unstructured":"Annapolis Microsystems, http:\/\/www.annapmicro.com , 2000"},{"key":"66_CR14","unstructured":"Virtual Computer Corp., http:\/\/www.vcc.com , 2000"},{"key":"66_CR15","doi-asserted-by":"crossref","unstructured":"Callahan, T., Hauser, J.R., Wawrzynek, J., \u201cThe Garp Architecture and C Compiler\u201d, IEEE Computer, April 2000","DOI":"10.1109\/2.839323"},{"key":"66_CR16","doi-asserted-by":"crossref","unstructured":"Li, Y., Callahan, T., Darnell, E., Harr, R., etal., \u201cHardware-Software Co-Design of Embedded Reconfigurable Architectures\u201d, Proc. 37th Design Automation Conference, 2000","DOI":"10.1145\/337292.337559"},{"key":"66_CR17","unstructured":"Gokhale, M.B., Stone, J.M., \u201cNAPAC: Compiling for a Hybrid RISC\/FPGA Machine\u201d, Proc. IEEE Symp. on FCCMs, 1998"},{"key":"66_CR18","doi-asserted-by":"crossref","unstructured":"Koch, A., Golze, U., \u201cPractical Experiences with the SPARXIL Co-Processor\u201d, Proc. Asilomar Conference on Signals, Systems, and Computers, 11\/1997","DOI":"10.1109\/ACSSC.1997.680267"},{"key":"66_CR19","unstructured":"Fung, J.M.L.F., Pan, J., \u201cConfigurable Cache\u201d, CMU EE742 course project, http:\/\/www.ece.cmu.edu\/ee742\/proj-s98\/fung , 1998"},{"key":"66_CR20","unstructured":"McKee, S.A., \u201cMaximizing Bandwidth for Streamed Computations\u201d, dissertation, U. of Virginia, School of Engineering and Applied Science, 1995"},{"key":"66_CR21","unstructured":"Sun Microelectronics, \u201cmicroSPARC-IIep User\u2019s Manual\u201d, http:\/\/www.sun.com\/sparc , 1997"},{"key":"66_CR22","unstructured":"Weaver, D.L., Germond, T., \u201cThe SPARC Architecture Manual, Version 8\u201d, Prentice-Hall, 1992"},{"key":"66_CR23","unstructured":"PLX Technology, \u201cPCI 9080 Data Book\u201d, http:\/\/www.plxtech.com , 1998"},{"key":"66_CR24","unstructured":"Xilinx, Inc., \u201cVirtex 2.5V Field-Programmable Gate Arrays\u201d, http:\/\/www.xilinx.com , 1999"},{"key":"66_CR25","unstructured":"Xilinx, Inc. \u201cDesigning Flexible, Fast CAMs with Virtex Family FPGAs\u201d, Xilinx Application Note 203, 1999"},{"key":"66_CR26","unstructured":"Hennessy, J., Patterson, D., \u201cComputer Architecture: A Quantitative Approach\u201d, Morgan-Kaumann, 1990"},{"key":"66_CR27","doi-asserted-by":"crossref","unstructured":"Zhong, P., Martonosi, M., \u201cUsing Reconfigurable Hardware to Customize Memory Hierarchies\u201d, Proc. SPIE, vol. 2914, 1996","DOI":"10.1117\/12.255821"},{"key":"66_CR28","unstructured":"Kimura, S., Yukishita, M., Itou, Y., et al., \u201cA Hardware\/Software Codesign Method for a General-Purpose Reconfigurable Co-Processor\u201d, Proc. 5th CODES\/CASHE, 1997"},{"key":"66_CR29","doi-asserted-by":"crossref","unstructured":"Carter, J., Hsieh, W., Stoller, L., et al., \u201cImpulse: Building a Smarter Memory Controller\u201d, Proc. 5th Intl. Symp. on High. Perf. Comp. Arch. (HPCA), 1999","DOI":"10.1109\/HPCA.1999.744334"},{"key":"66_CR30","doi-asserted-by":"crossref","unstructured":"Nakkar, M., Harding, J., Schwartz, D., et al., \u201cDynamically programmable cache\u201d, Proc. SPIE, vol. 3526, 1998","DOI":"10.1117\/12.327035"},{"key":"66_CR31","unstructured":"Zhang, X., Dasdan, A., Schulz, M., et al., \u201cArchitectural Adaptation for Application-Specific Locality Optimizations\u201d, Proc. Intl. Conf. on Comp. Design (ICCD), 1997"}],"container-title":["Lecture Notes in Computer Science","Field-Programmable Logic and Applications: The Roadmap to Reconfigurable Computing"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/3-540-44614-1_66","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,5,3]],"date-time":"2019-05-03T22:06:03Z","timestamp":1556921163000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/3-540-44614-1_66"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2000]]},"ISBN":["9783540678991","9783540446149"],"references-count":31,"URL":"https:\/\/doi.org\/10.1007\/3-540-44614-1_66","relation":{},"ISSN":["0302-9743"],"issn-type":[{"type":"print","value":"0302-9743"}],"subject":[],"published":{"date-parts":[[2000]]}}}