{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T23:37:39Z","timestamp":1725493059643},"publisher-location":"Berlin, Heidelberg","reference-count":9,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540678991"},{"type":"electronic","value":"9783540446149"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2000]]},"DOI":"10.1007\/3-540-44614-1_72","type":"book-chapter","created":{"date-parts":[[2007,10,20]],"date-time":"2007-10-20T13:25:22Z","timestamp":1192886722000},"page":"675-684","source":"Crossref","is-referenced-by-count":5,"title":["Exploiting Reconfigurability for Effective Detection of Delay Faults in LUT-Based FPGAs"],"prefix":"10.1007","author":[{"given":"Andrzej","family":"Krasniewski","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2002,4,12]]},"reference":[{"key":"72_CR1","doi-asserted-by":"crossref","unstructured":"Huang, W.K., Meyer, F. J., Chen X.-T., Lombardi, F.: Testing Configurable LUT-Based FPGA\u2019s. IEEE Trans. on VLSI Systems (1998) 276\u2013283","DOI":"10.1109\/92.678888"},{"key":"72_CR2","doi-asserted-by":"crossref","unstructured":"Renovell, M., Figueras, J., Zorian, Y.: Test of RAM-based FPGA: Methodology and Application to the Interconnect. Proc. 15th VLSI Test Symp. (1997) 230\u2013237","DOI":"10.1109\/VTEST.1997.600278"},{"key":"72_CR3","doi-asserted-by":"crossref","unstructured":"Stroud, C., Konala, S., Chen, P., Abramovici, M.: Built-In Self-Test of Logic Blocks in FPGAs (Finally, a Free Lunch: BIST Without Overhead!). Proc. 14th VLSI Test Symp. (1996) 387\u2013392","DOI":"10.1109\/VTEST.1996.510883"},{"key":"72_CR4","doi-asserted-by":"publisher","first-page":"16","DOI":"10.1109\/54.655178","volume":"1","author":"M. Leeser","year":"1998","unstructured":"Leeser M. et al.: Rothko \u2014 A Three-Dimensional FPGA. IEEE Design & Test of Computers 1 (1998) 16\u201323","journal-title":"IEEE Design & Test of Computers"},{"key":"72_CR5","unstructured":"Krasniewski, A.: Design for Application-Dependent Testability of FPGAs. Proc. Int\u2019l Workshop on Logic and Architecture Synthesis (1997) 245\u2013254"},{"key":"72_CR6","doi-asserted-by":"crossref","unstructured":"Krasniewski, A.: Application-Dependent Testing of FPGA Delay Faults. Proc. EUROMICRO\u201999 (1999) 260\u2013267","DOI":"10.1109\/EURMIC.1999.794478"},{"key":"72_CR7","doi-asserted-by":"crossref","unstructured":"Krasniewski, A.: Self-Testing of FPGA Delay Faults in the System Environment. Tech. Report, Warsaw Univ. of Technology, Inst. of Telecommunications (2000)","DOI":"10.1109\/OLT.2000.856610"},{"key":"72_CR8","unstructured":"Krasniewski, A.: Enhancing Detection of Delay Faults in FPGA-Based Circuits by Transformations of LUT Functions, Preprints IFAC Workshop on Programmable Devices and Systems \u2014 PDS2000 (2000) 127\u2013132"},{"key":"72_CR9","unstructured":"David R.: Random Testing of Digital Circuits \u2014 Theory and Applications, Marcel Dekker, Inc. (1998)"}],"container-title":["Lecture Notes in Computer Science","Field-Programmable Logic and Applications: The Roadmap to Reconfigurable Computing"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/3-540-44614-1_72","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,5,3]],"date-time":"2019-05-03T18:06:19Z","timestamp":1556906779000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/3-540-44614-1_72"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2000]]},"ISBN":["9783540678991","9783540446149"],"references-count":9,"URL":"https:\/\/doi.org\/10.1007\/3-540-44614-1_72","relation":{},"ISSN":["0302-9743"],"issn-type":[{"type":"print","value":"0302-9743"}],"subject":[],"published":{"date-parts":[[2000]]}}}