{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,19]],"date-time":"2025-03-19T13:22:33Z","timestamp":1742390553759},"publisher-location":"Berlin, Heidelberg","reference-count":6,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540678991"},{"type":"electronic","value":"9783540446149"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2000]]},"DOI":"10.1007\/3-540-44614-1_73","type":"book-chapter","created":{"date-parts":[[2007,10,20]],"date-time":"2007-10-20T13:25:22Z","timestamp":1192886722000},"page":"685-694","source":"Crossref","is-referenced-by-count":3,"title":["Dataflow Partitioning and Scheduling Algorithms for WASMII, a Virtual Hardware"],"prefix":"10.1007","author":[{"given":"Atsushi","family":"Takayama","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yuichiro","family":"Shibata","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Keisuke","family":"Iwai","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hideharu","family":"Amano","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2002,4,12]]},"reference":[{"key":"73_CR1","doi-asserted-by":"crossref","unstructured":"X.-P. Ling, H. Amano: \u201cWASMII: A Data Driven Computer on a Virtual Hardware\u201d Proc. FCCM\u2019 93, pp. 33\u201342, 1993.","DOI":"10.1109\/FPGA.1993.279481"},{"key":"73_CR2","unstructured":"K. Hiraki, T. Shimada, K. Nishida: \u201cA hardware design of the SIGMA-1: A data flow computer for scientific computations\u201d Proc. ICPP 1984."},{"key":"73_CR3","unstructured":"H. Miyazaki, Y. Shibata, A. Takayama, X. Ling and H. Amano: \u201cEmulation of Multichip WASMII on Reconfigurable System Testbed FLEMING\u201d PACT\u201998 Workshop on Reconfigurable Computing, pp. 47\u201352(1998)"},{"key":"73_CR4","unstructured":"http:\/\/www.kasahara.elec.waseda.ac.jp\/schedule\/apply_pe.ht ml (Prototype Task Graphs Generated from Real Application Programs)"},{"key":"73_CR5","unstructured":"Xilinx Inc.: \u201cThe Programmable Logic Data Book\u201d 1996."},{"key":"73_CR6","doi-asserted-by":"crossref","unstructured":"Karthikeya M.Gajjala Purna and Dinesh Bhatia: \u201cTemporal Partitioning and Scheduling Data Flow Graphs for Reconfigurable Computers\u201d IEEE Trans. Computers, Vol. 48, pp. 579\u2013590, June, 1999.","DOI":"10.1109\/12.773795"}],"container-title":["Lecture Notes in Computer Science","Field-Programmable Logic and Applications: The Roadmap to Reconfigurable Computing"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/3-540-44614-1_73","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,5,3]],"date-time":"2019-05-03T18:06:07Z","timestamp":1556906767000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/3-540-44614-1_73"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2000]]},"ISBN":["9783540678991","9783540446149"],"references-count":6,"URL":"https:\/\/doi.org\/10.1007\/3-540-44614-1_73","relation":{},"ISSN":["0302-9743"],"issn-type":[{"type":"print","value":"0302-9743"}],"subject":[],"published":{"date-parts":[[2000]]}}}