{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,19]],"date-time":"2025-03-19T13:47:53Z","timestamp":1742392073576,"version":"3.33.0"},"publisher-location":"Berlin, Heidelberg","reference-count":15,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540424994"},{"type":"electronic","value":"9783540446873"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2001]]},"DOI":"10.1007\/3-540-44687-7_19","type":"book-chapter","created":{"date-parts":[[2007,5,27]],"date-time":"2007-05-27T00:46:00Z","timestamp":1180226760000},"page":"182-191","source":"Crossref","is-referenced-by-count":28,"title":["Chip-Based Reconfigurable Task Management"],"prefix":"10.1007","author":[{"given":"Gordon","family":"Brebner","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Oliver","family":"Diessel","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2001,8,17]]},"reference":[{"issue":"1","key":"19_CR1","doi-asserted-by":"crossref","first-page":"68","DOI":"10.1109\/54.825678","volume":"17","author":"K. Bazargan","year":"2000","unstructured":"K. Bazargan, R. Kastner, and M. Sarrafzadeh. Fast template placement for reconfigurable computing systems. IEEE Design and Test of Computers, 17(1):68\u201383, Jan.-Mar. 2000.","journal-title":"IEEE Design and Test of Computers"},{"key":"19_CR2","series-title":"Lect Notes Comput Sci","doi-asserted-by":"crossref","first-page":"327","DOI":"10.1007\/3-540-61730-2_35","volume-title":"Proc. 6th International Workshop on Field Programmable Logic and Applications","author":"G. Brebner","year":"1996","unstructured":"G. Brebner. A virtual hardware operating system for the Xilinx XC6200. Proc. 6th International Workshop on Field Programmable Logic and Applications, Springer LNCS 1142, 1996, pages 327\u2013336."},{"key":"19_CR3","doi-asserted-by":"crossref","unstructured":"J. Burns, A. Donlin, J. Hogg, S. Singh, and M. de Wit. A dynamic reconfiguration run-time system. Proc. 5th Annual IEEE Symposium on FPGAs for Custom Computing Machines, IEEE, 1997, pages 66\u201375.","DOI":"10.1109\/FPGA.1997.624606"},{"key":"19_CR4","doi-asserted-by":"crossref","unstructured":"K. Compton, J. Cooley, S. Knol, and S. Hauck. Abstract: Configuration relocation and defragmentation for reconfigurable computing. Proc. 8th Annual IEEE Symposium on FPGAs for Custom Computing Machines, IEEE, 2000, pages 279\u2013280.","DOI":"10.1109\/FPGA.2000.903415"},{"key":"19_CR5","series-title":"Lect Notes Comput Sci","doi-asserted-by":"crossref","first-page":"131","DOI":"10.1007\/3-540-63465-7_218","volume-title":"Proc. 7th International Workshop on Field Programmable Logic and Applications","author":"O. Diessel","year":"1997","unstructured":"O. Diessel and H. ElGindy. Run-time compaction of FPGA designs. Proc. 7th International Workshop on Field Programmable Logic and Applications, Springer LNCS 1304, 1997, pages 131\u2013140."},{"key":"19_CR6","unstructured":"O. Diessel and H. ElGindy. On scheduling dynamic FPGA reconfigurations. Proc. Fifth Australasian Conference on Parallel and Real-Time Systems, Springer, 1998, pages 191\u2013200."},{"key":"19_CR7","series-title":"Lect Notes Comput Sci","doi-asserted-by":"crossref","first-page":"379","DOI":"10.1007\/3-540-44614-1_41","volume-title":"Proc. 10th International Workshop on Field Programmable Logic and Applications","author":"H. ElGindy","year":"2000","unstructured":"H. ElGindy, M. Middendorf, H. Schmeck, and B. Schmidt. Task rearrangement on partially reconfigurable FPGAs with restricted buffer. Proc. 10th International Workshop on Field Programmable Logic and Applications, Springer LNCS 1896, 2000, pages 379\u2013388."},{"key":"19_CR8","doi-asserted-by":"crossref","unstructured":"B. K. Gunther, G. J. Milne, and V. L. Narasimhan. Assessing document relevance with run-time reconfigurable machines. Proc. 4th Annual IEEE Symposium on FPGAs for Custom Computing Machines, IEEE, 1996, pages 10\u201317.","DOI":"10.1109\/FPGA.1996.564737"},{"key":"19_CR9","doi-asserted-by":"crossref","unstructured":"J. R. Hauser and J. Wawrzynek. Garp: A MIPS processor with a reconfigurable coprocessor. Proc. 5th Annual IEEE Symposium on FPGAs for Custom Computing Machines, IEEE, 1997, pages 12\u201321.","DOI":"10.1109\/FPGA.1997.624600"},{"key":"19_CR10","doi-asserted-by":"crossref","unstructured":"E. Lemoine and D. Merceron. Run time reconfiguration of FPGA for scanning genomic databases. Proc. 3rd Annual IEEE Symposium on FPGAs for Custom Computing Machines, IEEE, 1995, pages 90\u201398.","DOI":"10.1109\/FPGA.1995.477414"},{"key":"19_CR11","doi-asserted-by":"crossref","unstructured":"P. Lysaght, G. McGregor, and J. Stockwood. Configuration controller synthesis for dynamically reconfigurable systems. IEE Colloquium on Hardware-Software Cosynthesis for Reconfigurable Systems, IEE, 1996, pages 1\u20139.","DOI":"10.1049\/ic:19960228"},{"issue":"6","key":"19_CR12","doi-asserted-by":"crossref","first-page":"678","DOI":"10.1109\/12.277290","volume":"42","author":"R. Miller","year":"1993","unstructured":"R. Miller, V. K. Prasanna-Kumar, D. I. Reisis, and Q. F. Stout. Parallel computations on reconfigurable meshes. IEEE Transactions on Computers, 42(6):678\u2013692, June 1993.","journal-title":"IEEE Transactions on Computers"},{"key":"19_CR13","doi-asserted-by":"crossref","unstructured":"H. Schmit. Incremental reconfiguration for pipelined applications. Proc. 5th Annual IEEE Symposium on FPGAs for Custom Computing Machines, IEEE, 1997, pages 47\u201355.","DOI":"10.1109\/FPGA.1997.624604"},{"key":"19_CR14","series-title":"Lect Notes Comput Sci","doi-asserted-by":"crossref","first-page":"59","DOI":"10.1007\/BFb0055233","volume-title":"Proc. 8th International Workshop on Field Programmable Logic and Applications","author":"N. Shirazi","year":"1998","unstructured":"N. Shirazi, W. Luk, and P. Y. K. Cheung. Run-time management of dynamically reconfigurable designs. Proc. 8th International Workshop on Field Programmable Logic and Applications Springer LNCS 1482, 1998, pages 59\u201368."},{"key":"19_CR15","doi-asserted-by":"crossref","unstructured":"M. J. Wirthlin and B. L. Hutchings. Sequencing run-time reconfigured hardware with software. Proc. Fourth International ACM Symposium on Field Programmable Gate Arrays, ACM, 1996, pages 122\u2013128.","DOI":"10.1109\/FPGA.1996.242439"}],"container-title":["Lecture Notes in Computer Science","Field-Programmable Logic and Applications"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/3-540-44687-7_19","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,1,16]],"date-time":"2025-01-16T18:25:47Z","timestamp":1737051947000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/3-540-44687-7_19"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2001]]},"ISBN":["9783540424994","9783540446873"],"references-count":15,"URL":"https:\/\/doi.org\/10.1007\/3-540-44687-7_19","relation":{},"ISSN":["0302-9743"],"issn-type":[{"type":"print","value":"0302-9743"}],"subject":[],"published":{"date-parts":[[2001]]}}}