{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T21:09:40Z","timestamp":1725484180780},"publisher-location":"Berlin, Heidelberg","reference-count":13,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540424994"},{"type":"electronic","value":"9783540446873"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2001]]},"DOI":"10.1007\/3-540-44687-7_26","type":"book-chapter","created":{"date-parts":[[2007,5,27]],"date-time":"2007-05-27T00:46:00Z","timestamp":1180226760000},"page":"243-253","source":"Crossref","is-referenced-by-count":1,"title":["Gambit: A Tool for the Simultaneous Placement and Detailed Routing of Gate-Arrays"],"prefix":"10.1007","author":[{"given":"John","family":"Karro","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"James","family":"Cohoon","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2001,8,17]]},"reference":[{"unstructured":"Aho, A.V., Sethi, R., and Jeffery, U.D. Compilers: Principles, Techniques, and Tools. Addison-Wesley Publishing Company, 1986.","key":"26_CR1"},{"doi-asserted-by":"crossref","unstructured":"Alexander, M.J., Cohoon, J.P., Ganley, J.L., and Robins, G. Performance-oriented placement and routing for field-programmable gate arrays. Proceedings of the European Design Automation Conference, pages 80\u201385, 1995.","key":"26_CR2","DOI":"10.1109\/EURDAC.1995.527391"},{"issue":"12","key":"26_CR3","doi-asserted-by":"crossref","first-page":"1505","DOI":"10.1109\/43.552083","volume":"15","author":"M.J. Alexander","year":"1996","unstructured":"Alexander, M.J. and Robins, G. New Performance-Driven FPGA Routing Algorithms. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 15(12):1505\u20131517, December 1996.","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"doi-asserted-by":"crossref","unstructured":"Bapat, S. and Cohoon, J.P. A parallel VLSI circuit layout methodology. Proceedings of Sixth International Conference on VLSI Design, pages 236\u2013241, 1993.","key":"26_CR4","DOI":"10.1109\/ICVD.1993.669686"},{"doi-asserted-by":"crossref","unstructured":"Betz, V. and Rose, J. VPR: A New Packing, Placement and Routing Tool for FPGA Research. International Workshop on Field Programmable Logic and Applications, pages 213\u2013222, 1997.","key":"26_CR5","DOI":"10.1007\/3-540-63465-7_226"},{"doi-asserted-by":"crossref","unstructured":"D. Brelaz. New methods to color the vertices of a graph. Communications of the ACM, pages 251\u2013256, 1979.","key":"26_CR6","DOI":"10.1145\/359094.359101"},{"doi-asserted-by":"crossref","unstructured":"Karro, J. and Cohoon, J. A Spiffy Tool for the Simultaneous Placement and Global Routing of Three-Dimensional Field Programmable Gate Arrays. Ninth Great Lakes Symposium on VLSI, pages 226\u2013227, March 1999.","key":"26_CR7","DOI":"10.1109\/GLSV.1999.757418"},{"doi-asserted-by":"crossref","unstructured":"Lee, Y. and Wu, A. A performance and routability driven router for FPGA considering path delays. Proceedings of the 32 IEEE\/ACM Conference on Design Automation, pages 557\u2013561, 1995.","key":"26_CR8","DOI":"10.1145\/217474.217588"},{"doi-asserted-by":"crossref","unstructured":"Lesser, M., Meleis, W.M., Vai, M.M., and Zavracky, P.M. Rothko: A Three Dimensional FPGA Architecture, Its Fabrication, and Design Tools. Field-Programmable Logic and Applications, 1997.","key":"26_CR9","DOI":"10.1007\/3-540-63465-7_207"},{"issue":"5","key":"26_CR10","doi-asserted-by":"crossref","first-page":"499","DOI":"10.1109\/43.703831","volume":"17","author":"S.K. Nag","year":"1998","unstructured":"Nag, S.K. and Rutenbar, R.A. Performance-driven simultaneous place and route for FPGAs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 17(5):499\u2013518, June 1998.","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"doi-asserted-by":"crossref","unstructured":"Nakatake, S., Sakanushi, K., Kajitani, Y., and Kawakita, M. The channeled-BSG: a universal floorplan for simultaneous place\/route with IC applications. IEEE\/ACM International Conference on Computer-Aided Design, pages 418\u201325, 1998.","key":"26_CR11","DOI":"10.1145\/288548.289064"},{"doi-asserted-by":"crossref","unstructured":"Rose, J. Parallel Global Routing for Standard Cells. IEEE Transactions on Computer Aided Design, pages 1085\u20131095, October 1990.","key":"26_CR12","DOI":"10.1109\/43.62733"},{"doi-asserted-by":"crossref","unstructured":"Wu, Y.L. and Marek-Sadowska, M. Orthogonal Greedy Coupling-A New Optimization Approach to 2-D FPGA Routing. Proceedings of the ACM\/IEEE Design Automation Conference, pages 568\u2013573, 1995.","key":"26_CR13","DOI":"10.1145\/217474.217591"}],"container-title":["Lecture Notes in Computer Science","Field-Programmable Logic and Applications"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/3-540-44687-7_26","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,4,28]],"date-time":"2019-04-28T11:05:15Z","timestamp":1556449515000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/3-540-44687-7_26"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2001]]},"ISBN":["9783540424994","9783540446873"],"references-count":13,"URL":"https:\/\/doi.org\/10.1007\/3-540-44687-7_26","relation":{},"ISSN":["0302-9743"],"issn-type":[{"type":"print","value":"0302-9743"}],"subject":[],"published":{"date-parts":[[2001]]}}}