{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,1,17]],"date-time":"2025-01-17T05:20:30Z","timestamp":1737091230092,"version":"3.33.0"},"publisher-location":"Berlin, Heidelberg","reference-count":10,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540424994"},{"type":"electronic","value":"9783540446873"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2001]]},"DOI":"10.1007\/3-540-44687-7_30","type":"book-chapter","created":{"date-parts":[[2007,5,27]],"date-time":"2007-05-27T00:46:00Z","timestamp":1180226760000},"page":"286-295","source":"Crossref","is-referenced-by-count":1,"title":["Run-Time Optimized Reconfiguration Using Instruction Forecasting"],"prefix":"10.1007","author":[{"given":"Marios","family":"Iliopoulos","sequence":"first","affiliation":[]},{"given":"Theodore","family":"Antonakopoulos","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2001,8,17]]},"reference":[{"key":"30_CR1","doi-asserted-by":"crossref","unstructured":"Michael J. Wirthlin, Improving Functional Density Through Run-Time Circuit Reconfiguration, Ph.D. thesis, 1997.","DOI":"10.1145\/258305.258316"},{"key":"30_CR2","unstructured":"Xilinx, Application Note: Virtex Series Configuration Architecture User Guide, Virtex Series, XAPP151, v1.3, February 2000."},{"key":"30_CR3","unstructured":"Atmel, AT40K05\/10\/20\/40 FPGAs with DSP Optimized Core Cell and Distributed FreeRam, Datasheet, rev. 0896B-01\/99, January 1999."},{"key":"30_CR4","unstructured":"E. Tau, I. Eslick, D. Chen, J. Brown, and A. DeHon. A first generation DPGA implementation, Proceedings of the Third Canadian Workshop on Field-Programmable Devices, pages 138\u2013143, May 1995."},{"key":"30_CR5","doi-asserted-by":"crossref","unstructured":"Steve Trimberger, Dean Carberry, Anders Johnson, and Jennifer Wong. A time-multiplexed FPGA. In J. Arnold and K. L. Pocek, editors, Proceedings of the 5th IEEE Symposium on FPGAs for Custom Computing Machines, pages 22\u201328, Napa, CA, April 1997.","DOI":"10.1109\/FPGA.1997.624601"},{"key":"30_CR6","doi-asserted-by":"crossref","unstructured":"M.J. Wirthlin, and B.L. Hutchings, A Dynamic Instruction Set Computer, Proceedings of the 3rd IEEE Symposium on FPGAs for Custom Computing Machines (FCCM), 1995, pp. 99\u2013107.","DOI":"10.1109\/FPGA.1995.477415"},{"key":"30_CR7","unstructured":"Iliopoulos, M., Antonakopoulos, T., Optimized Reconfigurable MAC Processor Architecture, IEEE International Conference on Electronics and Computer Systems (ICECS), Malta, 2001."},{"key":"30_CR8","doi-asserted-by":"crossref","unstructured":"S. Hauck, Z. Li, and E. J. Schwabe. Configuration Compression for the Xilinx XC6200 FPGA, Proceedings of the 6th IEEE Symposium on FPGAs for Custom Computing Machines (FCCM), April 1998.","DOI":"10.1109\/FPGA.1998.707891"},{"key":"30_CR9","doi-asserted-by":"crossref","unstructured":"Iliopoulos, M., Antonakopoulos, T., A Methodology of Implementing Medium Access Protocols Using a General Parameterized Architecture, 11th IEEE International Workshop on Rapid System Prototyping (RSP), June 2000, Paris, France","DOI":"10.1109\/IWRSP.2000.854974"},{"key":"30_CR10","doi-asserted-by":"crossref","unstructured":"Iliopoulos, M., Antonakopoulos, T., Reconfigurable Network Processors based on Field Programmable System Level Integrated Circuits, 10th International Conference on Field Programmable Logic and Applications (FPL), Villach, Austria, August 2000.","DOI":"10.1007\/3-540-44614-1_5"}],"container-title":["Lecture Notes in Computer Science","Field-Programmable Logic and Applications"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/3-540-44687-7_30","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,1,16]],"date-time":"2025-01-16T18:25:55Z","timestamp":1737051955000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/3-540-44687-7_30"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2001]]},"ISBN":["9783540424994","9783540446873"],"references-count":10,"URL":"https:\/\/doi.org\/10.1007\/3-540-44687-7_30","relation":{},"ISSN":["0302-9743"],"issn-type":[{"type":"print","value":"0302-9743"}],"subject":[],"published":{"date-parts":[[2001]]}}}