{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T21:09:06Z","timestamp":1725484146741},"publisher-location":"Berlin, Heidelberg","reference-count":8,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540424994"},{"type":"electronic","value":"9783540446873"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2001]]},"DOI":"10.1007\/3-540-44687-7_36","type":"book-chapter","created":{"date-parts":[[2007,5,27]],"date-time":"2007-05-27T00:46:00Z","timestamp":1180226760000},"page":"346-356","source":"Crossref","is-referenced-by-count":3,"title":["Rapid Construction of Partial Configuration Datastreams from High-Level Constructs Using JBits"],"prefix":"10.1007","author":[{"given":"Satnam","family":"Singh","sequence":"first","affiliation":[]},{"given":"Philip","family":"James-Roxby","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2001,8,17]]},"reference":[{"key":"36_CR1","unstructured":"Singh, S and James-Roxby, P, \u201cLava and JBits: From HDL to Bitstream in Minutes\u201d, Proc. FCCM01, April, 2001, to be published"},{"key":"36_CR2","doi-asserted-by":"crossref","unstructured":"Brebner, G, \u201cThe Swappable Logic Unit: A Paradigm for Virtual Hardware\u201d, Proc. FCCM97, April, 1997, pp. 72\u201381","DOI":"10.1109\/FPGA.1997.624607"},{"key":"36_CR3","doi-asserted-by":"crossref","unstructured":"Luk, W, Shirazi, N and P. Cheung, \u201cCompilation Tools for Run-Time Reconfigurable Designs\u201d, Proc. FCCM97, April 1997, pp 56\u201365","DOI":"10.1109\/FPGA.1997.624605"},{"key":"36_CR4","doi-asserted-by":"crossref","unstructured":"Sezer, S et al, \u201cFast Partial Reconfiguration for FCCMs\u201d, Proc. FCCM98, pp. 318\u2013319","DOI":"10.1109\/FPGA.1998.707934"},{"key":"36_CR5","doi-asserted-by":"crossref","unstructured":"McMillan, S and Guccione, S, \u201cPartial Run-Time Reconfiguration Using JRTR\u201d, Proc. FPL 2000, Sept. 2000","DOI":"10.1007\/3-540-44614-1_38"},{"key":"36_CR6","unstructured":"Xilinx, Inc: \u201c Virtex Series Configuration Architecture User Guide\u201d, XAPP151, available on line at http:\/\/www.xilinx.com\/xapp\/xapp151.pdf , 2000"},{"key":"36_CR7","doi-asserted-by":"crossref","unstructured":"James-Roxby, P and Guccione, S, \u201cAutomated Extraction of Run-Time Parameterisable Cores from Programmable Device Configurations\u201d, Proc. FCCM00","DOI":"10.1109\/FPGA.2000.903402"},{"key":"36_CR8","doi-asserted-by":"crossref","unstructured":"Heron, J-P and Woods, R, \u201cAccelerating run-time reconfiguration on custom computing machines\u201d, Proc.SPIE International Symposium on Optical Science, Engineering and Instrumentation, San Diego, USA, 1998","DOI":"10.1117\/12.325718"}],"container-title":["Lecture Notes in Computer Science","Field-Programmable Logic and Applications"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/3-540-44687-7_36","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,4,28]],"date-time":"2019-04-28T11:04:31Z","timestamp":1556449471000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/3-540-44687-7_36"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2001]]},"ISBN":["9783540424994","9783540446873"],"references-count":8,"URL":"https:\/\/doi.org\/10.1007\/3-540-44687-7_36","relation":{},"ISSN":["0302-9743"],"issn-type":[{"type":"print","value":"0302-9743"}],"subject":[],"published":{"date-parts":[[2001]]}}}