{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,1,17]],"date-time":"2025-01-17T05:20:32Z","timestamp":1737091232158,"version":"3.33.0"},"publisher-location":"Berlin, Heidelberg","reference-count":11,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540424994"},{"type":"electronic","value":"9783540446873"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2001]]},"DOI":"10.1007\/3-540-44687-7_67","type":"book-chapter","created":{"date-parts":[[2007,5,27]],"date-time":"2007-05-27T00:46:00Z","timestamp":1180226760000},"page":"623-627","source":"Crossref","is-referenced-by-count":0,"title":["Initial Analysis of the Proteus Architecture"],"prefix":"10.1007","author":[{"given":"Michael","family":"Dales","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2001,8,17]]},"reference":[{"key":"67_CR1","unstructured":"ARM Ltd. ARM Architecture Reference Manual, DDI 0100D edition, 2000."},{"key":"67_CR2","doi-asserted-by":"crossref","unstructured":"Michael Dales. The Proteus Processor \u2014A Conventional CPU with Reconfigurable Functionality. In 9th International Workshop on Field Programmable Logic and Applications, pages 431\u2013437. Springer-Verlag, September 1999.","DOI":"10.1007\/978-3-540-48302-1_49"},{"key":"67_CR3","doi-asserted-by":"crossref","unstructured":"John R. Hauser and John Wawrzynek. GARP: A MIPS processor with a reconfigurable coprocessor. In J. Arnold and K. L. Pocek, editors, Proceedings of IEEE Workshop on FPGAsfor Custom Computing Machines, pages 12\u201321, Napa, CA, April 1997.","DOI":"10.1109\/FPGA.1997.624600"},{"key":"67_CR4","unstructured":"Infineon. Infineon introduces configurable CARMEL DSP Core for 3G wireless and broadband communication applications. Infineon Press Release, March 2000."},{"key":"67_CR5","unstructured":"Intel. Using MMX Instructions to Implement Audio Echo Sound Effects. Unpublished Technical Report, 2001."},{"key":"67_CR6","doi-asserted-by":"crossref","unstructured":"Rahul Razdan and Michael D. Smith. High-Performance Microarchitectures with Hardware-Programmable Functional Units. In Proc. 2 7th Annual IEEE\/ACM International Symposium on Microarchitecture, pages 172\u2013180, November 1994.","DOI":"10.1145\/192724.192749"},{"key":"67_CR7","unstructured":"S. Sawitzki, A. Gratz, and R. G. Spallek. CoMPARE: A Simple Reconfigurable Processor Architecture Exploiting Instruction Level Parallelism. In Proceedings of the 5th Australasian Conference on Parallel and Real-Time Systems, 1998."},{"key":"67_CR8","unstructured":"Bruce Schneier, John Kelsey, Doug Whiting, David Wagner, Chris Hall, and Niels Ferguson. Twofish: A 128-Bit Block Cipher, June 1998. AES Proposal."},{"key":"67_CR9","unstructured":"Sidsa. FIPSOC Mixed Signal System-on-Chip. SIDS A Semiconductor Design Solutions, 2000."},{"key":"67_CR10","unstructured":"Triscend. TriscendA7 Configurable System-on-Chip Family. Triscend Corporation, 2000."},{"key":"67_CR11","unstructured":"Xilinx. The Programmable Logic Data Book 1999. Xilinx, 1999."}],"container-title":["Lecture Notes in Computer Science","Field-Programmable Logic and Applications"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/3-540-44687-7_67","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,1,16]],"date-time":"2025-01-16T18:27:09Z","timestamp":1737052029000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/3-540-44687-7_67"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2001]]},"ISBN":["9783540424994","9783540446873"],"references-count":11,"URL":"https:\/\/doi.org\/10.1007\/3-540-44687-7_67","relation":{},"ISSN":["0302-9743"],"issn-type":[{"type":"print","value":"0302-9743"}],"subject":[],"published":{"date-parts":[[2001]]}}}