{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,1,17]],"date-time":"2025-01-17T05:20:30Z","timestamp":1737091230243,"version":"3.33.0"},"publisher-location":"Berlin, Heidelberg","reference-count":13,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540424994"},{"type":"electronic","value":"9783540446873"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2001]]},"DOI":"10.1007\/3-540-44687-7_8","type":"book-chapter","created":{"date-parts":[[2007,5,27]],"date-time":"2007-05-27T00:46:00Z","timestamp":1180226760000},"page":"70-80","source":"Crossref","is-referenced-by-count":0,"title":["Memory Synthesis for FPGA-Based Reconfigurable Computers"],"prefix":"10.1007","author":[{"given":"Amit","family":"Kasat","sequence":"first","affiliation":[]},{"given":"Iyad","family":"Ouaiss","sequence":"additional","affiliation":[]},{"given":"Ranga","family":"Vemuri","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2001,8,17]]},"reference":[{"key":"8_CR1","unstructured":"Xilinx Corporation. \u201cUsing Virtex BlockRAMs\u201d, 1999."},{"key":"8_CR2","unstructured":"Altera Corporation. \u201cFLEX 10K Embedded Programmable Logic Family Data Sheet\u201d, May 2000."},{"key":"8_CR3","unstructured":"Altera Corporation. \u201cAPEX 20K Programmable Logic Device Family Data Sheet\u201d, March 2000."},{"key":"8_CR4","doi-asserted-by":"crossref","unstructured":"P. Jha and N. Dutt. \u201cHigh-Level Library Mapping for Memories\u201d. In ACM Transactions on Design Automation of Electronic Systems, pages 566\u2013603. ACM Press, July 2000.","DOI":"10.1145\/348019.348297"},{"key":"8_CR5","doi-asserted-by":"crossref","unstructured":"M. Balakrishnan. \u201cAllocation of Multiport Memories in Data Path Synthesis\u201d. In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, volume 7, pages 536\u2013540, April 1998.","DOI":"10.1109\/43.3188"},{"key":"8_CR6","doi-asserted-by":"crossref","unstructured":"I. Ahmad and C. Y. Chen. \u201cPost-Process for Data Path Synthesis\u201d. In Proceedings of International Conference on Computer Aided Design, pages 276\u2013279. ACM Press, 1991.","DOI":"10.1109\/ICCAD.1991.185252"},{"key":"8_CR7","doi-asserted-by":"crossref","unstructured":"D. Karchmer and J. Rose. \u201cDefinition and Solution of the Memory Packing Problem for Field-Programmable Systems\u201d. In Proceedings of International Conference on Computer Aided Design, pages 20\u201326. ACM Press, November 1994.","DOI":"10.1109\/ICCAD.1994.629737"},{"key":"8_CR8","unstructured":"S. Wilton. \u201cArchitectures and Algorithms for Field-Programmable Gate Arrays with Embedded Memory\u201d. PhD thesis, University of Toronto, 1997."},{"key":"8_CR9","doi-asserted-by":"crossref","unstructured":"W. Ho and S. Wilton. \u201cLogical-to-Physical Memory Mapping for FPGAs with Dual-Port Embedded Arrays\u201d. In International Workshop on Field Programmable Logic and Applications, pages 111\u2013123, September 1999.","DOI":"10.1007\/978-3-540-48302-1_12"},{"key":"8_CR10","unstructured":"I. Ouaiss and R. Vemuri. \u201cHierarchical Memory Mapping During Synthesis in FPGA-Based Reconfigurable Computers\u201d. In Design Automation and Testing Conference of Europe, pages 284\u2013293, Berlin, Germany, September 2000. Springer-Verlag."},{"key":"8_CR11","unstructured":"I. Ouaiss and R. Vemuri. \u201cGlobal Memory Mapping During Synthesis in FPGA-Based Reconfigurable Computers\u201d. In Reconfigurable Architectures Workshop, pages 284\u2013293, San Francisco, September 2000. Springer-Verlag."},{"key":"8_CR12","doi-asserted-by":"crossref","unstructured":"F. Glover and M. Laguna. \u201cTabu Search\u201d. Kluwer Academic Publishers, 1997.","DOI":"10.1007\/978-1-4615-6089-0"},{"key":"8_CR13","doi-asserted-by":"crossref","unstructured":"I. Ouaiss and R. Vemuri. \u201cResource Arbitration in Reconfigurable Computing Environments\u201d. In Proceedings of Design Automation and Test in Europe, pages 560\u2013566. IEEE Computer Society Press, April 2000.","DOI":"10.1145\/343647.343856"}],"container-title":["Lecture Notes in Computer Science","Field-Programmable Logic and Applications"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/3-540-44687-7_8","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,1,16]],"date-time":"2025-01-16T18:26:20Z","timestamp":1737051980000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/3-540-44687-7_8"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2001]]},"ISBN":["9783540424994","9783540446873"],"references-count":13,"URL":"https:\/\/doi.org\/10.1007\/3-540-44687-7_8","relation":{},"ISSN":["0302-9743"],"issn-type":[{"type":"print","value":"0302-9743"}],"subject":[],"published":{"date-parts":[[2001]]}}}