{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,10]],"date-time":"2026-03-10T15:27:04Z","timestamp":1773156424330,"version":"3.50.1"},"publisher-location":"Berlin, Heidelberg","reference-count":17,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"value":"9783540425212","type":"print"},{"value":"9783540447092","type":"electronic"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2001]]},"DOI":"10.1007\/3-540-44709-1_8","type":"book-chapter","created":{"date-parts":[[2007,8,11]],"date-time":"2007-08-11T14:04:18Z","timestamp":1186841058000},"page":"77-92","source":"Crossref","is-referenced-by-count":58,"title":["Two Methods of Rijndael Implementation in Reconfigurable Hardware"],"prefix":"10.1007","author":[{"given":"Viktor","family":"Fischer","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Milo\u0161","family":"Drutarovsk\u00fd","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2001,9,20]]},"reference":[{"key":"8_CR1","unstructured":"Advanced Encryption Standard. http:\/\/www.nist.gov\/aes\/"},{"key":"8_CR2","unstructured":"Nechavatal, J. at al.: Report on the development of the Advanced Encryption Standard (AES). NIST [1], October (2000) 1\u2013116"},{"key":"8_CR3","series-title":"MD","first-page":"28","volume-title":"Proc. of The Third Advanced Encryption Standard Candidate Conference","author":"N. Weaver","year":"2000","unstructured":"Weaver, N., Wawrzynek, J.: A Comparison of the AES Candidates Amenability to FPGA Implementation. Proc. of The Third Advanced Encryption Standard Candidate Conference, NIST, Gaithersburg, MD, April 13\u201314, (2000) 28\u201339"},{"key":"8_CR4","series-title":"MD","first-page":"13","volume-title":"Proc. of The Third Advanced Encryption Standard Candidate Conference","author":"A. a. al. Elbirt","year":"2000","unstructured":"Elbirt, A. at al.: An FPGA Implementation and Performance Evaluation of the AES Block Cipher Candidate Algorithm Finalists. Proc. of The Third Advanced Encryption Standard Candidate Conference, NIST, Gaithersburg, MD, April 13\u201314, (2000) 13\u201327"},{"key":"8_CR5","series-title":"MD","first-page":"40","volume-title":"Proc. of The Third Advanced Encryption Standard Candidate Conference","author":"K. Gaj","year":"2000","unstructured":"Gaj, K., Chodowiec, P.: Comparison of the hardware performance of the AES candidates using reconfigurable hardware. Proc. of The Third Advanced Encryption Standard Candidate Conference, NIST, Gaithersburg, MD, April 13\u201314, (2000) 40\u201356."},{"key":"8_CR6","doi-asserted-by":"crossref","unstructured":"Danalis, A., Prasanna, V., Rolim, J.: A Comparative Study of Performance of AES Final Candidates Using FPGAs. Submission for The Third AES Candidate Conference, New York, March 21, 2000 available at [1]","DOI":"10.1007\/3-540-44499-8_9"},{"key":"8_CR7","unstructured":"Virtex series FPGAs. http:\/\/www.xilinx.com\/products\/virtex.com"},{"key":"8_CR8","unstructured":"Gaj, K., Chodowiec, P.: Hardware performance of the AES finalists-survey and analysis of results. Available at http:\/\/ece.gmu.edu\/crypto\/"},{"key":"8_CR9","unstructured":"Fischer, V.: Realization of the Round 2 Candidates using Altera FPGA. Submitted for The Third Advanced Encryption Standard Candidate Conference, New York, March 21, (2000), available at [1]"},{"key":"8_CR10","unstructured":"Bora, P., Czajka, T.: Implementation of the Serpent Algorithm Using Altera FPGA Devices. Public Comments on AES Candidate Algorithms-Round 2, available at [1]"},{"key":"8_CR11","unstructured":"Mroczowski, P.: Implementation of the block cipher Rijndael using Altera FPGA. Public Comments on AES Candidate Algorithms-Round 2, available at [1]"},{"key":"8_CR12","unstructured":"FLEX 10KE Embedded Programmable Logic Family. http:\/\/www.altera.com"},{"key":"8_CR13","unstructured":"Daemen, J., Rijmen, V.: AES Proposal: The Rijndael Block Cipher. Version 2, September (1999) 1-45, available at [1]"},{"key":"8_CR14","unstructured":"Fischer, V. Realisation of the RIJNDAEL Cipher in Field Programmable Devices. Proceedings of DCIS 2000, Montpellier, November (2000) 312\u2013317"},{"key":"8_CR15","unstructured":"ACEX 1K Programmable Logic Family. http:\/\/www.altera.com"},{"key":"8_CR16","unstructured":"APEX 20K Programmable Logic Family. http:\/\/www.altera.com"},{"key":"8_CR17","unstructured":"Chodowiec, P., Gaj, K. Implementation of the Twofish Cipher Using FPGA Devices. Technical Report, George Mason University, July (1999) 1\u201324, available at http:\/\/ece.gmu.edu\/crypto\/"}],"container-title":["Lecture Notes in Computer Science","Cryptographic Hardware and Embedded Systems \u2014 CHES 2001"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/3-540-44709-1_8","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,5,1]],"date-time":"2019-05-01T23:24:55Z","timestamp":1556753095000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/3-540-44709-1_8"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2001]]},"ISBN":["9783540425212","9783540447092"],"references-count":17,"URL":"https:\/\/doi.org\/10.1007\/3-540-44709-1_8","relation":{},"ISSN":["0302-9743"],"issn-type":[{"value":"0302-9743","type":"print"}],"subject":[],"published":{"date-parts":[[2001]]}}}