{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T21:01:48Z","timestamp":1725483708313},"publisher-location":"Berlin, Heidelberg","reference-count":5,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540425410"},{"type":"electronic","value":"9783540447986"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2001]]},"DOI":"10.1007\/3-540-44798-9_14","type":"book-chapter","created":{"date-parts":[[2007,5,3]],"date-time":"2007-05-03T13:16:15Z","timestamp":1178198175000},"page":"161-166","source":"Crossref","is-referenced-by-count":4,"title":["Specifying Hardware Timing with ET-Lotos"],"prefix":"10.1007","author":[{"given":"Ji","family":"He","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kenneth J.","family":"Turner","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2001,8,24]]},"reference":[{"key":"14_CR1","volume-title":"ISO\/IEC 8807","author":"ISO\/IEC.","year":"1989","unstructured":"ISO\/IEC. Information Processing Systems-Open Systems Interconnection-\n                  Lotos-A Formal Description Technique based on the Temporal Ordering of Observational Behaviour. ISO\/IEC 8807. International Organization for Standardization, Geneva, Switzerland, 1989."},{"key":"14_CR2","unstructured":"Ji He and Kenneth J. Turner. Dill (Digital Logic in Lotos) project web page. \n                    http:\/\/www.cs.stir.ac.uk\/~kjt\/research\/dill.html\n                    \n                  , November 2000."},{"key":"14_CR3","first-page":"483","volume-title":"Proc. Formal Description Techniques VI","author":"L. L\u00e9onard","year":"1994","unstructured":"Luc L\u00e9onard and Guy Leduc. An enhanced version of timed Lotos and its application to a case study. In Richard L. Tenney, Paul D. Amer, and M. \u00dcmit Uyar, editors, Proc. Formal Description Techniques VI, pages 483\u2013500. North-Holland, Amsterdam, Netherlands, 1994."},{"key":"14_CR4","volume-title":"Technical report","author":"L. Llana","year":"1995","unstructured":"Luis Llana and Gualberto Rabay Filho. Defining equivalences between time\/action graphs and timed action graphs. Technical report, Department of Telematic Systems Engineering, Polytechnic University of Madrid, Spain, December 1995."},{"key":"14_CR5","unstructured":"Gualberto Rabay Filho and Juan Quemada. TE-Lola: A timed Lola prototype. In Zmago Brezocnik and Tatjana Kapus, editors, Proc. COST 247 International Workshop on Applied Formal Methods, pages 85\u201395, Slovenia, June 1996. University of Maribor."}],"container-title":["Lecture Notes in Computer Science","Correct Hardware Design and Verification Methods"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/3-540-44798-9_14","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,2,16]],"date-time":"2019-02-16T07:35:33Z","timestamp":1550302533000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/3-540-44798-9_14"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2001]]},"ISBN":["9783540425410","9783540447986"],"references-count":5,"URL":"https:\/\/doi.org\/10.1007\/3-540-44798-9_14","relation":{},"ISSN":["0302-9743"],"issn-type":[{"type":"print","value":"0302-9743"}],"subject":[],"published":{"date-parts":[[2001]]}}}