{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,1,18]],"date-time":"2025-01-18T07:10:02Z","timestamp":1737184202210,"version":"3.33.0"},"publisher-location":"Berlin, Heidelberg","reference-count":18,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540419990"},{"type":"electronic","value":"9783540449423"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2001]]},"DOI":"10.1007\/3-540-44942-6_13","type":"book-chapter","created":{"date-parts":[[2007,6,9]],"date-time":"2007-06-09T04:25:09Z","timestamp":1181363109000},"page":"168-180","source":"Crossref","is-referenced-by-count":0,"title":["Improving the Performance of Heterogeneous DSMs via Multithreading"],"prefix":"10.1007","author":[{"given":"Renato J. O.","family":"Figueiredo","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jeffrey P.","family":"Bradford","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jos\u00e9 A. B.","family":"Fortes","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2001,5,11]]},"reference":[{"key":"13_CR1","unstructured":"Ben-Miled, Z. and Fortes, J.A.B. A Heterogeneous Hierarchical Solution to Cost-efficient High Performance Computing. Par. and Dist. Processing Symp.,Oct 1996."},{"key":"13_CR2","doi-asserted-by":"crossref","unstructured":"Boothe, B. and Ranade, A. Improved Multithreade Techniques for Hiding Communication Latency in Multiprocessors. In Proc. 19th International Symposium on Computer Architecture pages 214\u2013223,1992.","DOI":"10.1145\/146628.139729"},{"key":"13_CR3","doi-asserted-by":"crossref","unstructured":"Chrysos, George Z. and Emer, Joel S. Memory Dependence Prediction Using Store Sets. In Proc. 25th International Symposium on Computer Architecture pages 142\u2013153,1998.","DOI":"10.1109\/ISCA.1998.694770"},{"key":"13_CR4","doi-asserted-by":"crossref","unstructured":"Eggers, S.J., Emer, J.S., Levy, H.M., Lo, J.L., Stamm, R.L.,and Tullsen, D.M.Simultaneous Multithreading:A Platform for Next-Generation Processors. IEEE Micro pages 12\u201319, Sep.1997.","DOI":"10.1109\/40.621209"},{"key":"13_CR5","unstructured":"B.A. Gieseke et al. A 600MHz Superscalar RISC Microprocessor with Out-of-Order Execution.In International Solid State Circuits Conference1997."},{"key":"13_CR6","doi-asserted-by":"crossref","unstructured":"Figueiredo, R.J.O. and Fortes, J.A.B. Impact of Heterogeneity on DSM Performance. In Proc. 6 the International Symposium on High-Performance Computer Architecture pages 26\u201335, Jan 2000.","DOI":"10.1109\/HPCA.2000.824336"},{"key":"13_CR7","doi-asserted-by":"crossref","unstructured":"Gharachorloo, K., Lenoski, D., Laudon, J., Gibbons, P., Gupta, A.,and Hennessy, J. Memory Consistency and Event Ordering in Scalable Shared-memory Multi-processors.In Proc. 17th International Symposium Computer Architecture June 1990.","DOI":"10.1145\/325164.325102"},{"key":"13_CR8","doi-asserted-by":"crossref","unstructured":"Hammond, L., Nayfeh, B.A.,and Olukotun, K. A Single-Chip Multiprocessor. IEEE Computer Sep.1997.","DOI":"10.1109\/2.612253"},{"key":"13_CR9","unstructured":"Kroft, D. Lockup-Free Instruction Fetch\/Prefetch Cache Organization. In Proc. 8th International Symposium on Computer Architecture 1981."},{"key":"13_CR10","doi-asserted-by":"crossref","unstructured":"Pai, V.S., Ranganathan, P.,and Adve, S.V.The Impact of Instruction-Level Parallelism on Multiprocessor Performance an Simulation Methodology.In Proc. 3rd International Symposium on High-Performance Computer Architecture Feb 1997.","DOI":"10.1109\/HPCA.1997.569611"},{"key":"13_CR11","doi-asserted-by":"crossref","unstructured":"Papamarcos, M. and Patel, J. A Low Overhea Coherence Solution for Multi-processors with Private Cache Memories. In Proc. of 11th Annual Int. Symp. on Computer Architecture1984.","DOI":"10.1145\/800015.808204"},{"key":"13_CR12","doi-asserted-by":"crossref","unstructured":"Patt, Y.N., Patel, S.J., Evers, M., Friendly,D.H.,and Stark, J.One Billion Transistors,One Uniprocessor,One Chip.IEEE Computer pages 51\u201357, Sep. 1997.","DOI":"10.1109\/2.612249"},{"key":"13_CR13","unstructured":"Quinlan, J.R.C4.5: Programs for Machine LearningMorgan Kaufmann,San Mateo,California,1993."},{"key":"13_CR14","doi-asserted-by":"crossref","unstructured":"Reinman, G., Austin, T.,and Calder, B.A Scalable Front-end Architecture for Fast Instruction Delivery.In Proc. 26th International Symposium on Computer Architecture pages 234\u2013245,1999.","DOI":"10.1109\/ISCA.1999.765954"},{"key":"13_CR15","unstructured":"Semiconductor Industry Association.The National Technology Roadmap for Semiconductors.San Jose,CA,1997."},{"key":"13_CR16","unstructured":"Storino, S.N., Borkenhagen, J.M., Kalla, R.N.,and Kunkel, S.R. A Multi-Threade 64-bit PowerPC Commercial RISC Processor Design. In Hot Chips XI 1999."},{"key":"13_CR17","unstructured":"Wilton, S.J.E. and Jouppi, N.P. An Enhance Access an Cycle Time Model for On-Chip Caches.Technical Report WRL Research Report93\/5,Western Research Laboratory,Digital Equipment Corporation,1993."},{"key":"13_CR18","doi-asserted-by":"crossref","unstructured":"Woo, S.C.et al. The SPLASH-2 Programs:Characterization an Methodological Considerations.In Proceedings of the 22nd Annual Int. Symp. on Computer Architecture July 1995.","DOI":"10.1145\/223982.223990"}],"container-title":["Lecture Notes in Computer Science","Vector and Parallel Processing \u2014 VECPAR 2000"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/3-540-44942-6_13","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,1,17]],"date-time":"2025-01-17T04:17:50Z","timestamp":1737087470000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/3-540-44942-6_13"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2001]]},"ISBN":["9783540419990","9783540449423"],"references-count":18,"URL":"https:\/\/doi.org\/10.1007\/3-540-44942-6_13","relation":{},"ISSN":["0302-9743"],"issn-type":[{"type":"print","value":"0302-9743"}],"subject":[],"published":{"date-parts":[[2001]]}}}