{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,4,3]],"date-time":"2025-04-03T09:03:46Z","timestamp":1743671026487,"version":"3.38.0"},"publisher-location":"Berlin, Heidelberg","reference-count":26,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540404088"},{"type":"electronic","value":"9783540449898"}],"license":[{"start":{"date-parts":[[2003,1,1]],"date-time":"2003-01-01T00:00:00Z","timestamp":1041379200000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2003]]},"DOI":"10.1007\/3-540-44989-2_88","type":"book-chapter","created":{"date-parts":[[2010,11,19]],"date-time":"2010-11-19T22:10:02Z","timestamp":1290204602000},"page":"737-744","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":7,"title":["Review of Capacitive Threshold Gate Implementations"],"prefix":"10.1007","author":[{"given":"V.","family":"Beiu","sequence":"first","affiliation":[]},{"given":"M. J.","family":"Avedillo","sequence":"additional","affiliation":[]},{"given":"J. M.","family":"Quintana","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2003,6,18]]},"reference":[{"key":"88_CR1","unstructured":"V. Beiu, J.M. Quintana and M.J. Avedillo: \u201cVLSI Implementations of Threshold Logic: A Survey\u201d accepted for publication at IEEE Trans. on Neural Networks special number on Hardware Implementations."},{"key":"88_CR2","unstructured":"J. R. Burns, N.J. Trenton and R.A. Powlus, \u201cThreshold circuit utilizing field effect transistors\u201d, U.S: Patent 3 260 863, Jul. 12, 1966."},{"key":"88_CR3","first-page":"1444","volume":"SC-39","author":"T. Shibata","year":"1992","unstructured":"T. Shibata, and T. Ohmi, \u201cA functional MOS transistor featuring gate-level weighted sum and threshold operations,\u201d IEEE J. Solid-State Circuits, vol. SC-39, pp. 1444\u20131455, June 1992.","journal-title":"IEEE J. Solid-State Circuits"},{"key":"88_CR4","unstructured":"T. Shibata, \u201cIntelligent VLSI Systems Based on a Psychological Brain Model\u201d, Proceedings IEEE International Symposium on intelligent Signal Processing and Systems, pp. 323\u2013332, November 2000."},{"key":"88_CR5","doi-asserted-by":"publisher","first-page":"570","DOI":"10.1109\/16.199362","volume":"ED-40","author":"T. Shibata","year":"1993","unstructured":"T. Shibata, and T. Ohmi, \u201cNeuron MOS binary-logic integrated circuits\u2014Part I: Design fundamentals and soft-hardware-logic circuit implementation,\u201d IEEE Trans. Electron Devices, vol. ED-40, pp. 570\u2013576, Mar. 1993.","journal-title":"IEEE Trans. Electron Devices"},{"key":"88_CR6","doi-asserted-by":"publisher","first-page":"974","DOI":"10.1109\/16.210207","volume":"ED-40","author":"T. Shibata","year":"1993","unstructured":"T. Shibata, and T. Ohmi, \u201cNeuron MOS binary-logic integrated circuits-Part II: Simplifying techniques of circuit configuration and their practical applications,\u201d IEEE Trans. Electron Devices, vol. ED-40, pp. 974\u2013979, May 1993.","journal-title":"IEEE Trans. Electron Devices"},{"key":"88_CR7","doi-asserted-by":"publisher","first-page":"102","DOI":"10.1109\/82.913193","volume":"CAS2-48","author":"E. Rodr\u00edguez-Villegas","year":"2001","unstructured":"E. Rodr\u00edguez-Villegas, G. Huertas, M.J. Avedillo, J.M. Quintana, and A. Rueda, \u201cA practical floating-gate Muller-C element using vMOS threshold gates,\u201d IEEE Trans. Circuits Syst. II, vol. CAS2-48, pp. 102\u2013106, Jan. 2001.","journal-title":"IEEE Trans. Circuits Syst. II"},{"issue":"7","key":"88_CR8","first-page":"924","volume":"E80-C","author":"H. Y. Kwon","year":"1997","unstructured":"H. Y. Kwon, K. Kotani, T. Shibata and T. Ohmi: \u201cLow Power Neuron-MOS Technology for High-Functionality Logic Gate Synthesis\u201d, IEICE Trans. Electron., Vol. E80-C, No. 7, pp. 924\u2013929, Jul. 1997.","journal-title":"IEICE Trans. Electron."},{"key":"88_CR9","doi-asserted-by":"crossref","unstructured":"K. Kotani, T. Shibata, M. Imai, and T. Ohmi, \u201cClocked-neuron-MOS logic circuits employing auto-threshold-adjustment,\u201d Proc. ISSCC\u201995, San Francisco (USA), 1995, pp. 320\u2013321, 388","DOI":"10.1109\/ISSCC.1995.535583"},{"key":"88_CR10","doi-asserted-by":"publisher","first-page":"518","DOI":"10.1109\/82.663810","volume":"CAS2-45","author":"K. Kotani","year":"1998","unstructured":"K. Kotani, T. Shibata, M. Imai, and T. Ohmi, \u201cClocked-controlled neuron-MOS logic gates,\u201d IEEE Trans. Circuits Syst. II, vol. CAS2-45, pp. 518\u2013522, Apr. 1998.","journal-title":"IEEE Trans. Circuits Syst. II"},{"key":"88_CR11","doi-asserted-by":"crossref","unstructured":"R. Lashevsky, K. Takaara and M. Souma, \u201cNeuron MOSFET as a way to design a hreshold gates with the threshold and input weigths alterable in real time\u201d, Proc APCCAS\u201998, Chiangmai (Thailand), 1998, pp. 263\u2013266.","DOI":"10.1109\/APCCAS.1998.743739"},{"key":"88_CR12","unstructured":"W. Weber, S. Prange, R. Thewes, and E. Wohlrab, \u201cA neuron MOS transistor-based multiplier cell,\u201d in IEDM Technical Digest, 1995, pp. 21.5.1\u201321.5.4."},{"key":"88_CR13","doi-asserted-by":"publisher","first-page":"1700","DOI":"10.1109\/16.536816","volume":"ED-43","author":"W. Weber","year":"1996","unstructured":"W. Weber, S.J. Prange, R. Thewes, E. Wohlrab, and A. Luck, \u201cOn the application of Neuron MOS transistor principle for modern VLSI design,\u201d IEEE Trans. Electron Devices, vol. ED-43, pp. 1700\u20131708, Oct. 1996.","journal-title":"IEEE Trans. Electron Devices"},{"key":"88_CR14","unstructured":"H. Y. Huang, and T.N. Wang, \u201cCMOS capacitor coupling logic (C 3 L) logic circuits,\u201d Proc. Asia Pacific pp. 33\u201336 AP-ASIC, Cheju (Korea), 2000, pp. 33\u201336."},{"issue":"17","key":"88_CR15","doi-asserted-by":"publisher","first-page":"1067","DOI":"10.1049\/el:20010742","volume":"37","author":"P. Celinski","year":"2001","unstructured":"P. Celinski, J.F. L\u00f3pez, S. Al-Sarawi, and D. Abbott, \u201cLow power, high speed, charge recycling CMOS threshold logic gate,\u201d Electron. Lett., vol. 37, no. 17, pp. 1067\u20131069, Aug. 2001.","journal-title":"Electron. Lett."},{"key":"88_CR16","doi-asserted-by":"publisher","first-page":"2157","DOI":"10.1049\/el:19951471","volume":"31","author":"M. J. Avellido","year":"1995","unstructured":"M. J. Avellido, J.M. Quintana, A. Rueda, and E. Jim\u00e9nez, \u201cA low-power CMOS threshold-gate,\u201d Electron. Lett., vol. 31, pp. 2157\u20132159, Dec. 1995.","journal-title":"Electron. Lett."},{"key":"88_CR17","doi-asserted-by":"crossref","unstructured":"P. Celinski. S. Al-Sarawi, D. Abbot, J.F. Lopez, \u201cLow depth carry lookahead adder addition using charge recycling threshold logic,\u201d Proc. ISCAS 2002, pp. 469\u2013472, Scottsdale (USA).","DOI":"10.1109\/ISCAS.2002.1009879"},{"issue":"13","key":"88_CR18","doi-asserted-by":"publisher","first-page":"633","DOI":"10.1049\/el:20020438","volume":"38","author":"P. Celinski","year":"2002","unstructured":"P. Celinski, J.F. L\u00f3pez, S. Al-Sarawi and D. Abbott, \u201cCompact parallel (m, n) Counters based on Self-Timed Threshold Logic\u201d, Electronics Letters, Vol. 38, No. 13, pp. 633\u2013635, Jun 2002.","journal-title":"Electronics Letters"},{"key":"88_CR19","doi-asserted-by":"publisher","first-page":"958","DOI":"10.1049\/el:19870674","volume":"23","author":"Y. P. Tsividis","year":"1987","unstructured":"Y. P. Tsividis, and D. Anastassiou, \u201cSwitched-capacitor neural networks,\u201d Electron. Lett., vol. 23, pp. 958\u2013959, mo. 1987.","journal-title":"Electron. Lett."},{"key":"88_CR20","doi-asserted-by":"crossref","first-page":"210","DOI":"10.1109\/31.68299","volume":"CAS2-38","author":"U. \u00c7ilingiroglu","year":"1991","unstructured":"U. \u00c7ilingiroglu, \u201cA purely capacitive synaptic matrix for fixed-weight neural networks,\u201d IEEE Trans. Circuits Syst. II, vol. CAS2-38, pp. 210\u2013217, Apr. 1991.","journal-title":"IEEE Trans. Circuits Syst. II"},{"key":"88_CR21","doi-asserted-by":"publisher","first-page":"1141","DOI":"10.1109\/4.508261","volume":"SC-31","author":"H. \u00d6zdemir","year":"1996","unstructured":"H. \u00d6zdemir, A. Kepkep, B. Pamir, Y. Leblebici, and U. \u00c7ilingiroglu, \u201cA capacitive threshold-logic gate,\u201d IEEE J. Solid-State Circuits, vol. SC-31, pp. 1141\u20131150, Aug. 1996.","journal-title":"IEEE J. Solid-State Circuits"},{"key":"88_CR22","first-page":"105","volume":"2","author":"Y. Leblebici","year":"1998","unstructured":"Y. Leblebici, F.K. G\u00fcrkaynak, and D. Mlynek, \u201cA compact 31-input programmable majority gate based on capacitive threshold logic,\u201d Proc. International Symposium on Circuits and Systems ISCAS\u201998, Monterey (USA), vol. 2, 1998, pp. 105\u2013108.","journal-title":"Proc. International Symposium on Circuits and Systems ISCAS\u201998"},{"key":"88_CR23","doi-asserted-by":"crossref","unstructured":"A. Stokman, S. Cotofan\u00e3, and S. Vassiliadis, \u201cA versatile threshold logic gate,\u201d Proc. Annual Semiconductor Conference CAS\u201998, Sinaia, (Romania), 1998, pp. 163\u2013166.","DOI":"10.1109\/SMICND.1998.732326"},{"key":"88_CR24","unstructured":"J. L\u00f3pez Garcia, J. Fernandez Ramos, and A. Gago Boh\u00f3rquez, \u201cA balanced capacitive threshold logic gate,\u201d Proc. Design of Circuits and Integrated Systems (DCIS\u20192000), Montpellier (France), 2000."},{"key":"88_CR25","doi-asserted-by":"publisher","first-page":"1231","DOI":"10.1109\/16.842967","volume":"ED-47","author":"A. Luck","year":"2000","unstructured":"A. Luck, S. Jung, R. Brederlow, R. Thewes, K, Goser, and W. Weber, \u201cOn the design robustness of threshold logic gates using multi-input floating gate MOS transistors,\u201d IEEE Trans. Electron Devices, vol. ED-47, pp. 1231\u20131240, Jun. 2000.","journal-title":"IEEE Trans. Electron Devices"},{"issue":"7","key":"88_CR26","doi-asserted-by":"publisher","first-page":"978","DOI":"10.1109\/4.772413","volume":"34","author":"S. Jung","year":"1999","unstructured":"S. Jung, R. Thewes, T. Scheiter, K.F. Goser, and W. Weber, \u201cA low-power and high per formance CMOS fingerprint sensing and encoding architecture\u201d, IEEE Journal of Solid State Circuits, Vol. 34, no. 7, pp. 978\u2013984, Jul. 1999.","journal-title":"IEEE Journal of Solid State Circuits"}],"container-title":["Lecture Notes in Computer Science","Artificial Neural Networks and Neural Information Processing \u2014 ICANN\/ICONIP 2003"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/3-540-44989-2_88","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,2,28]],"date-time":"2025-02-28T02:52:33Z","timestamp":1740711153000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/3-540-44989-2_88"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2003]]},"ISBN":["9783540404088","9783540449898"],"references-count":26,"URL":"https:\/\/doi.org\/10.1007\/3-540-44989-2_88","relation":{},"ISSN":["0302-9743"],"issn-type":[{"type":"print","value":"0302-9743"}],"subject":[],"published":{"date-parts":[[2003]]},"assertion":[{"value":"18 June 2003","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}}]}}