{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,28]],"date-time":"2025-10-28T00:26:46Z","timestamp":1761611206455},"publisher-location":"Berlin, Heidelberg","reference-count":37,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540417811"},{"type":"electronic","value":"9783540452454"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2001]]},"DOI":"10.1007\/3-540-45245-1_5","type":"book-chapter","created":{"date-parts":[[2007,7,2]],"date-time":"2007-07-02T18:06:02Z","timestamp":1183399562000},"page":"63-80","source":"Crossref","is-referenced-by-count":6,"title":["PROPAN: A Retargetable System for Postpass Optimisations and Analyses"],"prefix":"10.1007","author":[{"given":"Daniel","family":"K\u00e4stner","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2001,7,20]]},"reference":[{"key":"5_CR1","unstructured":"Analog Devices. ADSP-2106x SHARC User\u2019s Manual, 1995."},{"key":"5_CR2","doi-asserted-by":"crossref","unstructured":"Siamak Arya. An Optimal Instruction Scheduling Model for a Class of Vector Processors. IEEE Transactions on Computers, 1985.","DOI":"10.1109\/TC.1985.1676531"},{"key":"5_CR3","unstructured":"S. Bashford and R. Leupers. Phase-Coupled Mapping of Data Flow Graphs to Irregular Data Paths. DAES, pages 1\u201350, 1999."},{"key":"5_CR4","unstructured":"F. Bodin, Z. Chamski, E. Rohou, and A. Seznec. Functional Specification of SALTO: A Retargetable System for Assembly Language Transformation and Optimization. rev. 1.00 beta. INRIA, 1997."},{"key":"5_CR5","unstructured":"E. Farquhar and E. Hadad. TriCore Architecture Manual. Siemens AG, 1997."},{"key":"5_CR6","doi-asserted-by":"crossref","unstructured":"A. Fauth, J. Van Praet, and M. Freericks. Describing Instruction Set Processors Using nML. In Proceedings of the EDAC, pages 503\u2013507. IEEE, 1995.","DOI":"10.1109\/EDTC.1995.470354"},{"key":"5_CR7","doi-asserted-by":"crossref","unstructured":"C. Ferdinand. Cache Behavior Prediction for Real-Time Systems. PhD thesis, Saarland University, 1997.","DOI":"10.1007\/BFb0057777"},{"key":"5_CR8","doi-asserted-by":"crossref","unstructured":"C. Ferdinand, D. K\u00e4stner, M. Langenbach, F. Martin, M. Schmidt, J. Schneider, J. Theiling, S. Thesing, and R. Wilhelm. Run-Time Guarantees for Real-Time Systems-The USES Approach. Proceedings of the ATPS, 1999.","DOI":"10.1007\/978-3-662-01069-3_60"},{"key":"5_CR9","doi-asserted-by":"crossref","unstructured":"J.A. Fisher. Trace Scheduling: A Technique for Global Microcode Compaction. IEEE Transactions on Computers, pages 478\u2013490, 1981.","DOI":"10.1109\/TC.1981.1675827"},{"key":"5_CR10","doi-asserted-by":"crossref","unstructured":"C.H. Gebotys and M.I. Elmasry. Global Optimization Approach for Architectural Synthesis. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pages 1266\u20131278, 1993.","DOI":"10.1109\/43.240074"},{"key":"5_CR11","doi-asserted-by":"crossref","unstructured":"R. Govindarajan, Erik R. Altman, and Guang R. Gao. A Framework for Resource Constrained Rate Optimal Software Pipelining. IEEE Transactions on Parallel and Distributed Systems, (11), 1996.","DOI":"10.1109\/71.544355"},{"key":"5_CR12","unstructured":"G. Hadjiyiannis. ISDL: Instruction Set Description Language Version 1.0. Technical report, MIT RLE, 1998."},{"key":"5_CR13","doi-asserted-by":"crossref","unstructured":"A. Halambi, P. Grun, V. Ganesh, Khare A., N. Dutt, and A. Nicolau. EXPRESSION: A Language for Architecture Exploration through Compiler\/Simulator Retargetability. DATE, 1999.","DOI":"10.1145\/307418.307549"},{"key":"5_CR14","doi-asserted-by":"crossref","unstructured":"Silvina Hanono and Srinivas Devadas. Instruction Scheduling, Resource Allocation, and Scheduling in the AVIV Retargetable Code Generator. In Proceedings of the DAC. ACM, 1998.","DOI":"10.1145\/277044.277184"},{"key":"5_CR15","unstructured":"ILOG S.A. ILOG CPLEX 6.5 User\u2019s Manual, 1999."},{"key":"5_CR16","unstructured":"D. K\u00e4stner. TDL: A Hardware and Assembly Description Language. Technical Report TDL1.4, TFB 14, Saarland University, 2000."},{"key":"5_CR17","unstructured":"D. K\u00e4stner and M. Langenbach. Integer Linear Programming vs. Graph-Based Methods in Code Generation. Technical report, Saarland University, 1998."},{"key":"5_CR18","doi-asserted-by":"crossref","unstructured":"D. K\u00e4stner and M. Langenbach. Code Optimization by Integer Linear Programming. In Proceedings of the CC, pages 122\u2013136, 1999.","DOI":"10.1007\/978-3-540-49051-7_9"},{"key":"5_CR19","doi-asserted-by":"crossref","unstructured":"D. K\u00e4stner and S. Thesing. Cache Sensitive Pre-Runtime Scheduling. In Proceedings of the LCTES Workshop, 1998.","DOI":"10.1007\/BFb0057786"},{"key":"5_CR20","doi-asserted-by":"crossref","unstructured":"Daniel K\u00e4stner. Retargetable Code Optimization by Integer Linear Programming. PhD thesis, Saarland University, 2000. To appear.","DOI":"10.1007\/978-3-540-49051-7_9"},{"key":"5_CR21","unstructured":"K\u00e4stner, D. and Wilhelm, R. Operations research methods in compiler backends. Mathematical Communications, 1999."},{"key":"5_CR22","unstructured":"M. Langenbach. CRL \u2014 A Uniform Representation for Control Flow. Technical Report CRL1, TFB 14, Saarland University, November 1998."},{"key":"5_CR23","doi-asserted-by":"crossref","unstructured":"Rainer Leupers. Retargetable Code Generation for Digital Signal Processors. Kluwer Academic Publishers, 1997.","DOI":"10.1007\/978-1-4757-2570-4"},{"key":"5_CR24","unstructured":"R. Lipsett, C. Schaefer, and C. Ussery. VHDL: Hardware Description and Design. Kluwer Academic Publishers, 12. edition, 1993."},{"key":"5_CR25","unstructured":"Peter Marwedel and Gert Goossens. Code Generation for Embedded Processors. Kluwer, 1995."},{"key":"5_CR26","series-title":"Lect Notes Comput Sci","first-page":"16","volume-title":"Languages and Compilers for Parallel Computing","author":"S. Novack","year":"1994","unstructured":"S. Novack and A. Nicolau. Mutation scheduling: A Unified Approach to Compiling for fine-grain Parallelism. In Languages and Compilers for Parallel Computing, pages 16\u201330. Springer LNCS, 1994."},{"key":"5_CR27","doi-asserted-by":"crossref","unstructured":"L. Nowak. Graph Based Retargetable Microcode Compilation in the MIMOLA Design System. 20th Annual Workshop on Microprogramming, pages 126\u2013132, 1987.","DOI":"10.1145\/255305.255329"},{"key":"5_CR28","doi-asserted-by":"crossref","unstructured":"S. Pees, A. Hoffmann, V. Zivojnovic, and H. Meyr. LISA: Machine Description Language for Cycle-Accurate Models of Programmable DSP Architectures. Proceedings of the DAC, 1999.","DOI":"10.1145\/309847.310101"},{"key":"5_CR29","unstructured":"Philips Electronics North America Corporation. TriMedia TM1000 Preliminary Data Book, 1997."},{"key":"5_CR30","doi-asserted-by":"crossref","unstructured":"John Ruttenberg, G.R. Gao, A. Stoutchinin, and W. Lichtenstein. Software Pipelining Showdown: Optimal vs. Heuristic Methods in a Production Compiler. Proceedings of the PLDI, pages 1\u201311, 1996.","DOI":"10.1145\/249069.231385"},{"key":"5_CR31","doi-asserted-by":"crossref","unstructured":"M.A.R. Saghir, P. Chow, and C.G. Lee. Exploiting Dual Data-Memory Banks in Digital Signal Processors. Proceedings of the ASPLOS, 1996.","DOI":"10.1145\/237090.237193"},{"key":"5_CR32","unstructured":"Ashok Sudarsanam. Code Optimization Libraries For Retargetable Compilation For Embedded Digital Signal Processors. PhD thesis, University of Princeton, 1998."},{"key":"5_CR33","unstructured":"Texas Instruments. TMS320C62xx Programmer\u2019s Guide, 1997."},{"key":"5_CR34","unstructured":"Reinhard Wilhelm and Dieter Maurer. Compiler Design. Addison-Wesley, 1995."},{"key":"5_CR35","unstructured":"H.P. Williams. Model Building in Mathematical Programming. John Wiley and Sons, 1993."},{"key":"5_CR36","unstructured":"L. Zhang. SILP. Scheduling and Allocating with Integer Linear Programming. PhD thesis, Saarland University, 1996."},{"key":"5_CR37","unstructured":"V. Zivojnovic, J. M. Velarde, C. Schl\u00e4ger, and H. Meyr. DSPSTONE: A DSP-Oriented Benchmarking Methodology. In Proceedings of the International Conference on Integrated Systems for Signal Processing, 1994."}],"container-title":["Lecture Notes in Computer Science","Languages, Compilers, and Tools for Embedded Systems"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/3-540-45245-1_5","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,4,30]],"date-time":"2019-04-30T01:38:11Z","timestamp":1556588291000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/3-540-45245-1_5"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2001]]},"ISBN":["9783540417811","9783540452454"],"references-count":37,"URL":"https:\/\/doi.org\/10.1007\/3-540-45245-1_5","relation":{},"ISSN":["0302-9743"],"issn-type":[{"type":"print","value":"0302-9743"}],"subject":[],"published":{"date-parts":[[2001]]}}}