{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,5,8]],"date-time":"2025-05-08T18:22:12Z","timestamp":1746728532663},"publisher-location":"Berlin, Heidelberg","reference-count":20,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540418610"},{"type":"electronic","value":"9783540453062"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2001]]},"DOI":"10.1007\/3-540-45306-7_20","type":"book-chapter","created":{"date-parts":[[2007,10,27]],"date-time":"2007-10-27T22:55:18Z","timestamp":1193525718000},"page":"289-303","source":"Crossref","is-referenced-by-count":9,"title":["Speculative Prefetching of Induction Pointers"],"prefix":"10.1007","author":[{"given":"Artour","family":"Stoutchinin","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jos\u00e9 Nelson","family":"Amaral","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Guang R.","family":"Gao","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"James C.","family":"Dehnert","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Suneel","family":"Jain","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Alban","family":"Douillet","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2001,3,23]]},"reference":[{"key":"20_CR1","doi-asserted-by":"publisher","first-page":"609","DOI":"10.1109\/12.381947","volume":"44","author":"T. F. Chen","year":"1995","unstructured":"T. F. Chen and J. L. Baer. Effective hardware-based data prefetching for high-performance processors. IEEE Transactions on Computers, 44:609\u2013623, May 1995.","journal-title":"IEEE Transactions on Computers"},{"issue":"12","key":"20_CR2","doi-asserted-by":"publisher","first-page":"67","DOI":"10.1109\/2.889095","volume":"33","author":"T. M. Chilimbi","year":"2000","unstructured":"T. M. Chilimbi, M. D. Hill, and J. R. Larus. Making pointer-based data structures cache conscious. Computer, 33(12):67\u201374, December 2000.","journal-title":"Computer"},{"key":"20_CR3","doi-asserted-by":"crossref","unstructured":"F. Chow, S. Chan, R. Kennedy, S-M Liu, R. Lo, and Peng Tu. A new algorithm for partial redundancy elimination based on SSA form. In International Conference on Programming Languages Design and Implementation, pages 273\u2013286, 1997.","DOI":"10.1145\/258915.258940"},{"key":"20_CR4","volume-title":"Introduction to Algorithms","author":"T. H. Cormen","year":"1990","unstructured":"T. H. Cormen, C. E. Leiserson, and R. L. Rivest. Introduction to Algorithms. MIT Press; McGraw-Hill Book Company, Cambridge, Massachusetts; New York, New York, 1990."},{"key":"20_CR5","doi-asserted-by":"publisher","first-page":"181","DOI":"10.1007\/BF01205184","volume":"7","author":"J. C. Dehnert","year":"1993","unstructured":"J. C. Dehnert and R. A. Towle. Compiling for the cydra 5. The Journal of Supercomputing, 7:181\u2013227, May 1993.","journal-title":"The Journal of Supercomputing"},{"key":"20_CR6","doi-asserted-by":"crossref","unstructured":"J. Fu and J. Patel. Stride directed prefetching in scalar processors. In International Symposium on Microarchitecture, pages 102\u2013110, 1992.","DOI":"10.1109\/MICRO.1992.697004"},{"key":"20_CR7","doi-asserted-by":"crossref","unstructured":"J. Gonzales and A. Gonzales. Speculative execution via address prediction and data prefetching. In International Conference on Supercomputing, pages 196\u2013203, 1997.","DOI":"10.1145\/263580.263631"},{"key":"20_CR8","doi-asserted-by":"crossref","unstructured":"M. Lipasti, W. Schmidt, S. Kunkel, and R. Roediger. SPAID: Software prefetching in pointer-and call-intensive environments. In International Symposium on Microarchitecture, pages 231\u2013236, 1995.","DOI":"10.1109\/MICRO.1995.476830"},{"key":"20_CR9","doi-asserted-by":"crossref","unstructured":"C. K. Luk and T. Mowry. Compiler based prefetching for recursive data structures. In International Conference on Architectural Support for Programming Languages and Operating Systems, pages 222\u2013233, 1996.","DOI":"10.1145\/237090.237190"},{"key":"20_CR10","doi-asserted-by":"crossref","unstructured":"S. Mantripragada, S. Jain, and J. Dehnert. A new framework for integrated global local scheduling. In Conference on Parallel Architectures and Compilation Techniques, pages 167\u2013174, Paris, France, October 1998.","DOI":"10.1109\/PACT.1998.727189"},{"key":"20_CR11","unstructured":"S. Mehrotra. Data Prefetch Mechanisms for Accelerating Symbolic and Numeric Computation. PhD thesis, University of Illinois at Urbana-Champaign, 1996."},{"key":"20_CR12","unstructured":"T. Mowry. Tolerating Latency Through Software-Controlled Data Prefetching. PhD thesis, Stanford University, 1994."},{"key":"20_CR13","doi-asserted-by":"crossref","unstructured":"T. Mowry and C. K. Luk. Predicting data cache misses in non-numeric applications through correlation profiling. In International Symposium on Microarchitecture, pages 314\u2013320, 1997.","DOI":"10.1109\/MICRO.1997.645827"},{"key":"20_CR14","doi-asserted-by":"crossref","unstructured":"T. Ozawa, Y. Kimura, and S. Nishizaki. Cache miss heuristics and preloading techniques for general-purpose programs. In International Symposium on Microarchitecture, pages 243\u2013248, 1995.","DOI":"10.1109\/MICRO.1995.476832"},{"key":"20_CR15","unstructured":"B. Rau. Iterative modulo scheduling. Technical Report HPL-94-115, HP Laboratories, 1995."},{"key":"20_CR16","doi-asserted-by":"crossref","unstructured":"A. Roth, A. Moshovos, and G. Sohi. Dependence based prefetching for linked data structures. In International Conference on Architectural Support for Programming Languages and Operating Systems, pages 115\u2013126, 1998.","DOI":"10.1145\/291069.291034"},{"key":"20_CR17","doi-asserted-by":"crossref","unstructured":"J. Ruttenberg, G. R. Gao, A. Stouchinin, and W. Lichtenstein. Software pipelining showdown: Optimal vs. heuristic methods in a production compiler. In International Conference on Programming Languages Design and Implementation, pages 1\u201311, Philadelphia, PA, May 1996.","DOI":"10.1145\/231379.231385"},{"key":"20_CR18","unstructured":"C. Selvidge. Compilation-Based Prefetching for Memory Latency Tolerance. PhD thesis, MIT, 1992."},{"key":"20_CR19","unstructured":"A. Stoutchinin, J. N. Amaral, G. R. Gao, J. Dehnert, and S. Jain. Automatic prefetching of induction pointers for software pipelining. Technical Report 37, November 1999."},{"issue":"3","key":"20_CR20","doi-asserted-by":"publisher","first-page":"211","DOI":"10.1137\/0202017","volume":"2","author":"R. Tarjan","year":"1973","unstructured":"R. Tarjan. Enumeration of the elementary circuits of a directed graph. SIAM Journal on Computing, 2(3):211\u2013216, September 1973.","journal-title":"SIAM Journal on Computing"}],"container-title":["Lecture Notes in Computer Science","Compiler Construction"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/3-540-45306-7_20","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,5,4]],"date-time":"2019-05-04T02:19:38Z","timestamp":1556936378000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/3-540-45306-7_20"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2001]]},"ISBN":["9783540418610","9783540453062"],"references-count":20,"URL":"https:\/\/doi.org\/10.1007\/3-540-45306-7_20","relation":{},"ISSN":["0302-9743"],"issn-type":[{"type":"print","value":"0302-9743"}],"subject":[],"published":{"date-parts":[[2001]]}}}