{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,19]],"date-time":"2025-03-19T12:00:38Z","timestamp":1742385638983},"publisher-location":"Berlin, Heidelberg","reference-count":15,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540430094"},{"type":"electronic","value":"9783540453079"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2001]]},"DOI":"10.1007\/3-540-45307-5_17","type":"book-chapter","created":{"date-parts":[[2007,8,16]],"date-time":"2007-08-16T07:10:12Z","timestamp":1187248212000},"page":"192-203","source":"Crossref","is-referenced-by-count":7,"title":["Weld: A Multithreading Technique Towards Latency-tolerant VLIW Processors"],"prefix":"10.1007","author":[{"given":"Emre","family":"\u00d6zer","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Thomas M.","family":"Conte","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Saurabh","family":"Sharma","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2001,12,4]]},"reference":[{"unstructured":"P. K. Dubey, K. O\u2019Brien, K. M. O\u2019Brien and C. Barton, \u201cSingle-Program Speculative Multithreading (SPSM) Architecture: Compiler-Assisted Fine-Grained Multithreading,\u201d in Proc. Int\u2019l Conf. Parallel Architecture and Compilation Techniques. (Cyprus). June 1995.","key":"17_CR1"},{"doi-asserted-by":"crossref","unstructured":"H. Akkary and M. A. Driscoll, \u201cA Dynamic Multithreading Processor,\u201d in Proc. 31st Ann. Int\u2019l Symp. Microarchitecture, Nov. 1998.","key":"17_CR2","DOI":"10.1109\/MICRO.1998.742784"},{"doi-asserted-by":"crossref","unstructured":"G. S. Sohi, S. E. Breach and T. N. Vijaykumar, \u201c Multiscalar Processors,\u201d in Proc.22nd Ann. Int\u2019l Symp. Computer Architecture. (Italy). May 1995.","key":"17_CR3","DOI":"10.1145\/223982.224451"},{"doi-asserted-by":"crossref","unstructured":"S. Wallace, B. Calder and D. M. Tullsen, \u201cThreaded Multiple Path Execution,\u201d in Proc. 25th Ann. Int\u2019l Symp. Computer Architecture, Barcelona, Spain, June 1998.","key":"17_CR4","DOI":"10.1109\/ISCA.1998.694778"},{"doi-asserted-by":"crossref","unstructured":"D. M. Tullsen, S. J. Eggers and H. M. Levy, \u201cSimultaneous Multithreading: Maximizing On-chip Parallelism,\u201d in Proc. 22nd Ann. Int\u2019l Symp. Computer Architecture, Italy, May 1995.","key":"17_CR5","DOI":"10.1145\/223982.224449"},{"unstructured":"G. Prasadh and C. Wu, \u201cA Benchmark Evaluation of a Multithreaded RISC Processor Architecture,\u201d in Proc. of Int\u2019l Conf. on Parallel Processing, Aug. 1991.","key":"17_CR6"},{"doi-asserted-by":"crossref","unstructured":"S. W. Keckler and W. J. Dally, \u201cProcessor Coupling: Integrating Compile Time and Runtime Scheduling for Parallelism,\u201d in Proc. 19th Ann. Int\u2019l Symp. Computer Architecture, Australia, May 1992.","key":"17_CR7","DOI":"10.1145\/139669.139728"},{"doi-asserted-by":"crossref","unstructured":"M. Fillo, S. W. Keckler, W. J. Dally, N.P. Carter, A. Chang, Y. Gurevich and W.S. Lee, \u201cThe M-Machine Multicomputer,\u201d in Proc.28th Ann. Int\u2019l Symp. Microarchitecture, Ann Arbor, MI, Dec. 1995.","key":"17_CR8","DOI":"10.1109\/MICRO.1995.476822"},{"doi-asserted-by":"crossref","unstructured":"A. Wolfe and J.P. Shen,\u201c A Variable Instruction Stream Extension to the VLIW Architecture,\u201d in Proc. 4th Int\u2019l Conf. on Architectural Support for Programming Languages and Operating Systems, ACM Press, Apr. 1991.","key":"17_CR9","DOI":"10.1145\/106972.106976"},{"unstructured":"W. A. Havanki, \u201cTreegion Scheduling for VLIW Processors\u201d, Master\u2019s Thesis, Dept. of Electrical and Computer Engineering, North Carolina State University, Raleigh, NC 27695-7911, July 1997.","key":"17_CR10"},{"unstructured":"W. A. Havanki, S. Banerjia and T. M. Conte, \u201cTreegion Scheduling for Wideissue Processors\u201d, in Proc. 4th Int\u2019l Symp. High Performance Computer Architecture, Las Vegas NV, Feb. 1998.","key":"17_CR11"},{"doi-asserted-by":"crossref","unstructured":"B. R. Rau, \u201cDynamically Scheduled VLIW Processors,\u201d Proc. 26th Ann. Int\u2019l Symp. Microarchitecture, Dec 1993.","key":"17_CR12","DOI":"10.1109\/MICRO.1993.282744"},{"doi-asserted-by":"crossref","unstructured":"J. E. Smith and A. R. Pleszkun, \u201cImplementing Precise Interrupts in Pipelined Processors\u201d, in IEEE Trans. on Computers, Vol. 37, NO. 5, May 1988.","key":"17_CR13","DOI":"10.1109\/12.4607"},{"doi-asserted-by":"crossref","unstructured":"M. Franklin and G. S. Sohi, \u201cThe Expandable Split Window Paradigm for Exploiting Fine-grain Parallelism\u201d, Proc. 19th Ann. Int\u2019l Symp. Computer Architecture, Gold Coast, Australia, May 1992.","key":"17_CR14","DOI":"10.1109\/ISCA.1992.753304"},{"doi-asserted-by":"crossref","unstructured":"M. Franklin and G. S. Sohi, \u201cARB: A Hardware Mechanism for Dynamic Reordering of Memory References\u201d, in IEEE Trans. on Computers, May 1996.","key":"17_CR15","DOI":"10.1109\/12.509907"}],"container-title":["Lecture Notes in Computer Science","High Performance Computing \u2014 HiPC 2001"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/3-540-45307-5_17","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,2,21]],"date-time":"2019-02-21T17:53:56Z","timestamp":1550771636000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/3-540-45307-5_17"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2001]]},"ISBN":["9783540430094","9783540453079"],"references-count":15,"URL":"https:\/\/doi.org\/10.1007\/3-540-45307-5_17","relation":{},"ISSN":["0302-9743"],"issn-type":[{"type":"print","value":"0302-9743"}],"subject":[],"published":{"date-parts":[[2001]]}}}