{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,1,17]],"date-time":"2025-01-17T05:21:07Z","timestamp":1737091267336,"version":"3.33.0"},"publisher-location":"Berlin, Heidelberg","reference-count":34,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540410683"},{"type":"electronic","value":"9783540453734"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2000]]},"DOI":"10.1007\/3-540-45373-3_10","type":"book-chapter","created":{"date-parts":[[2007,5,28]],"date-time":"2007-05-28T05:29:50Z","timestamp":1180330190000},"page":"88-107","source":"Crossref","is-referenced-by-count":2,"title":["A Holistic Approach to System Level Energy Optimization"],"prefix":"10.1007","author":[{"given":"Mary","family":"Jane Irwin","sequence":"first","affiliation":[]},{"given":"Mahmut","family":"Kandemir","sequence":"additional","affiliation":[]},{"given":"N.","family":"Vijaykrishnan","sequence":"additional","affiliation":[]},{"given":"Anand","family":"Sivasubramaniam","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2001,9,28]]},"reference":[{"key":"10_CR1","unstructured":"J. Bunda, W. C. Athas, and D. Fussell. Evaluating power implication of CMOS microprocessor design decisions. In Proc. the 1994 International Workshop on Low Power Design, April 1994."},{"key":"10_CR2","doi-asserted-by":"crossref","unstructured":"R. Y. Chen, R. M. Owens, and M. J. Irwin. Validation of an architectural level power analysis technique. In Proc. the 35th Design Automation Conference, June 1998.","DOI":"10.1145\/277044.277106"},{"key":"10_CR3","doi-asserted-by":"crossref","unstructured":"G. Esakkimuthu, N. Vijaykrishnan, M. Kandemir, and M. J. Irwin. Memory system energy: Influence of hardware-software optimizations. In Proc. ACM\/IEEE International Symposium on Low Power Electronics and Design, Rapallo\/Portofino Coast, Italy, July, 2000.","DOI":"10.1109\/LPE.2000.155291"},{"key":"10_CR4","doi-asserted-by":"crossref","unstructured":"M. Kandemir, N. Vijaykrishnan, M. J. Irwin, and H. S. Kim. Towards energy-awareiteration space tiling. In Proc. the Workshop on Languages, Compilers, and Tools for Embedded Systems, Vancouver, B.C., June, 2000.","DOI":"10.1007\/3-540-45245-1_16"},{"key":"10_CR5","doi-asserted-by":"crossref","unstructured":"M. Kandemir, N. Vijaykrishnan, M. J. Irwin, and W. Ye. Influence of Compiler Optimizations on System Power. Submitted to IEEE Transactions on VLSI, March 2000.","DOI":"10.1145\/337292.337425"},{"key":"10_CR6","unstructured":"M. Wolfe. High Performance Compilers for Parallel Computing, Addison Wesley, CA, 1996."},{"key":"10_CR7","doi-asserted-by":"crossref","unstructured":"W. Ye, N. Vijaykrishnan, M. Kandemir, and M. J. Irwin. The design and use of SimplePower: a cycle-accurate energy estimation tool. In Proc. the 37th Design Automation Conference, Los Angeles, CA, June 5\u20139, 2000.","DOI":"10.1145\/337292.337436"},{"key":"10_CR8","unstructured":"G. Albera and R. I. Bahar. Power and performance tradeoffs using various cache configurations. In Proc. Power Driven Micro-architecture Workshop, in conjunction with ISCA\u201998, Barcelona, Spain, June 1998."},{"key":"10_CR9","doi-asserted-by":"crossref","unstructured":"D. H. Albonesi. Selective cache ways: On-demand cache resource allocation. In Proc. the 32nd International Symposium on Microarchitecture, pp. 248\u2013259, November 1999.","DOI":"10.1109\/MICRO.1999.809463"},{"key":"10_CR10","doi-asserted-by":"crossref","unstructured":"F. Balasa, F. Catthoor, and H. De Man. Exact evaluation of memory area for multi-dimensional processing systems. In Proc. the IEEE International Conference on Computer Aided Design, Santa Clara, CA, pages 669\u2013672, November 1993.","DOI":"10.1109\/ICCAD.1993.580159"},{"key":"10_CR11","doi-asserted-by":"crossref","unstructured":"D. Brooks, V. Tiwari, and M. Martonosi. Wattch: A framework for architecturallevel power analysis and optimizations. In Proc the 27th International Symposium on Computer Architecture, Vancouver, British Columbia, June 2000.","DOI":"10.1145\/339647.339657"},{"issue":"9","key":"10_CR12","doi-asserted-by":"crossref","first-page":"1277","DOI":"10.1109\/4.535411","volume":"31","author":"R. Gonzales","year":"1996","unstructured":"R. Gonzales and M. Horowitz. Energy dissipation in general purpose processors. IEEE Journal of Solid-State Circuits, 31(9):1277\u20131283, Sept 1996.","journal-title":"IEEE Journal of Solid-State Circuits"},{"key":"10_CR13","doi-asserted-by":"crossref","unstructured":"M. K. Gowan, L. L. Biro, and D. B. Jackson. Power considerations in the desing of the Alpha 21264 microprocessor. In Proc. the Design Automation Conference, San Francisco, CA, 1998.","DOI":"10.1145\/277044.277226"},{"key":"10_CR14","doi-asserted-by":"crossref","unstructured":"N. Vijaykrishnan, M. Kandemir, M. J. Irwin, H. Y. Kim, and W. Ye. Energydriven integrated hardware-software optimizations using SimplePower. In Proc. the International Symposium on Computer Architecture, Vancouver, British Columbia, June 2000.","DOI":"10.1145\/339647.339659"},{"key":"10_CR15","doi-asserted-by":"crossref","unstructured":"K. Roy and M. C. Johnson. Software design for low power. Low Power Design in Deep Sub-micron Electronics, Kluwer Academic Press, October 1996, Edt. J. Mermet and W. Nebel, pp. 433\u2013459.","DOI":"10.1007\/978-1-4615-5685-5_15"},{"key":"10_CR16","unstructured":"M. J. Irwin and N. Vijaykrishnan. Low-power design: From soup to nuts. Tutorial Notes, ISCA, 2000."},{"key":"10_CR17","unstructured":"V. Zyuban and P. Kogge. Inherently lower-power high-performance superscalar architectures, submitted to IEEE Transactions on Computers."},{"key":"10_CR18","doi-asserted-by":"crossref","unstructured":"J. Kin et al. The filter cache: An energy efficient memory structure. In Proc. International Symposium on Microarchitecture, December 1997.","DOI":"10.1109\/MICRO.1997.645809"},{"key":"10_CR19","doi-asserted-by":"crossref","unstructured":"C.-L. Su and A. M. Despain. Cache design trade-offs for power and performance optimization: A case study, In Proc. International Symposium on Low Power Electronics and Design, pp. 63\u201368, 1995.","DOI":"10.1145\/224081.224093"},{"key":"10_CR20","doi-asserted-by":"crossref","unstructured":"M. B. Kamble and K. Ghose. Analytical energy dissipation models for low power caches. In Proc. International Symposium on Low Power Electronics and Design, pages 143\u2013148, 1997.","DOI":"10.1145\/263272.263310"},{"key":"10_CR21","doi-asserted-by":"crossref","unstructured":"K. Itoh, K. Sasaki, and Y. Nakagome. Trends in low-power ram circuit technologies. Proceedings of the IEEE, pages 524\u2013543, Vol. 83. No. 4, April 1995.","DOI":"10.1109\/5.371965"},{"key":"10_CR22","doi-asserted-by":"crossref","unstructured":"L. Benini, A. Bogliolo, S. Cavallucci, and B. Ricco. Monitoring system activity for os directed dynamic power management. In Proceedings of the International Symposium on Low Power Electronics and Design, pages 185\u2013190, 1998.","DOI":"10.1145\/280756.280887"},{"key":"10_CR23","doi-asserted-by":"crossref","unstructured":"D. Burger and T. Austin. The simplescalar tool set, version 2.0. Technical report, Computer Sciences Department, University of Wisconsin, June, 1997.","DOI":"10.1145\/268806.268810"},{"key":"10_CR24","unstructured":"R. Y. Chen, R. M. Owens, and M. J. Irwin. Architectural level power estimation and design experiments. To appear in ACM Transactions on Design Automation of Electronic Systems."},{"key":"10_CR25","doi-asserted-by":"crossref","unstructured":"R. Y. Chen, R. M. Owens, and M. J. Irwin. Validation of an architectural level power analysis technique. In Proceedings of the 35th Design Automation Conference, pages 242\u2013245, June 1998.","DOI":"10.1145\/277044.277106"},{"key":"10_CR26","unstructured":"F. Douglis, P. Krishnan, and B. Marsh. Thwarting the power-hungry disk. In Proceedings of the 1994 Winter USENIX Conference, pages 293\u2013306, January 1994."},{"key":"10_CR27","doi-asserted-by":"crossref","unstructured":"J. Flinn and M. Satyanarayanan. Powerscope: A tool for profiling the energy usage of mobile applications. In Proceedings of the 2nd IEEE Workshop on Mobile Computing Systems and Applications, 1999.","DOI":"10.1109\/MCSA.1999.749272"},{"key":"10_CR28","doi-asserted-by":"crossref","unstructured":"J. Hezavei, N. Vijaykrishnan, and M. J. Irwin. A comparative study of power efficient SRAM designs. In to appear in Proc. of Great Lakes Symposium on VLSI, 2000.","DOI":"10.1145\/330855.331018"},{"key":"10_CR29","doi-asserted-by":"crossref","unstructured":"K. Inoue, T. Ishihara, and K. Murakami. Way-predicting set-associative cache for high performance and low energy consumption. In Proceedings of the International Symposium on Low Power Electronics and Design, pages 273\u2013275, 1999.","DOI":"10.1145\/313817.313948"},{"key":"10_CR30","doi-asserted-by":"crossref","unstructured":"M. J. Irwin and N. Vijaykrishnan. Energy issues in multimedia systems. In Proc. of Workshop on Signal Processing System, pages 24\u201333, October 1999.","DOI":"10.1109\/SIPS.1999.822304"},{"issue":"4","key":"10_CR31","doi-asserted-by":"crossref","first-page":"524","DOI":"10.1109\/5.371965","volume":"83","author":"K. Itoh","year":"1995","unstructured":"K. Itoh, K. Sasaki, and Y. Nakagome. Trends in low-power ram circuit technologies. Proceedings of IEEE, 83(4):524\u2013543, April 1995.","journal-title":"Proceedings of IEEE"},{"key":"10_CR32","unstructured":"K. Li, R. Kumpf, P. Horton, and T. Anderson. A quantitative analysis of disk drive power management in portable computers. In Proceedings of the 1994 Winter USENIX Conference, pages 279\u2013292, January 1994."},{"key":"10_CR33","doi-asserted-by":"crossref","unstructured":"J. R. Lorch and A. J. Smith. Software strategies for portable computer energy management. IEEE Personal Communications, pages 60\u201373, June 1998.","DOI":"10.1109\/98.683740"},{"key":"10_CR34","doi-asserted-by":"crossref","unstructured":"M. Wolf and M. Lam. A data locality optimizing algorithm. In Proceedings of ACM SIGPLAN 91 Conference Programming Language Design and Implementation, pages 30\u201344, June 1991.","DOI":"10.1145\/113445.113449"}],"container-title":["Lecture Notes in Computer Science","Integrated Circuit Design"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/3-540-45373-3_10","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,1,16]],"date-time":"2025-01-16T18:35:32Z","timestamp":1737052532000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/3-540-45373-3_10"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2000]]},"ISBN":["9783540410683","9783540453734"],"references-count":34,"URL":"https:\/\/doi.org\/10.1007\/3-540-45373-3_10","relation":{},"ISSN":["0302-9743"],"issn-type":[{"type":"print","value":"0302-9743"}],"subject":[],"published":{"date-parts":[[2000]]}}}