{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T21:08:51Z","timestamp":1725484131709},"publisher-location":"Berlin, Heidelberg","reference-count":7,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540410683"},{"type":"electronic","value":"9783540453734"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2000]]},"DOI":"10.1007\/3-540-45373-3_14","type":"book-chapter","created":{"date-parts":[[2007,5,28]],"date-time":"2007-05-28T05:29:50Z","timestamp":1180330190000},"page":"139-148","source":"Crossref","is-referenced-by-count":1,"title":["Impact of Voltage Scaling on Glitch Power Consumption"],"prefix":"10.1007","author":[{"given":"Henrik","family":"Eriksson","sequence":"first","affiliation":[]},{"given":"Per","family":"Larsson-Edefors","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2001,9,28]]},"reference":[{"key":"14_CR1","doi-asserted-by":"crossref","unstructured":"J. Leijten, J. van Meerbergen, and J. Jess, \u201cAnalysis and Reduction of Glitches in Synchronous Networks\u201d, in Proceedings of the 1995 European Design and Test Conference, 1995, pp. 398\u2013403.","DOI":"10.1109\/EDTC.1995.470365"},{"key":"14_CR2","doi-asserted-by":"crossref","unstructured":"S. Kim and S.-Y. Hwang, \u201cEfficient Algorithm for Glitch Power Reduction\u201d, Electronics Letters, vol. 35, no. 13, pp. 1040\u20131041, June 1999.","DOI":"10.1049\/el:19990765"},{"key":"14_CR3","doi-asserted-by":"crossref","unstructured":"A. Raghunathan, S. Dey, and N. K. Jha, \u201cRegister Transfer Level Power Optimization with Emphasis on Glitch Analysis and Reduction\u201d, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 18, no. 8, pp. 1114\u20131131, Aug. 1999.","DOI":"10.1109\/43.775632"},{"key":"14_CR4","volume-title":"International Technology Roadmap for Semiconductors: 1999 edition","author":"Semiconductor Industry Association","year":"1999","unstructured":"Semiconductor Industry Association, International Technology Roadmap for Semiconductors: 1999 edition, Austin, TX:International SEMATECH, 1999."},{"key":"14_CR5","doi-asserted-by":"crossref","unstructured":"B. Davari, \u201cCMOS Technology: Present and Future\u201d, in Digest of Technical Papers, 1999 Symposium on VLSI Circuits, 1999, pp. 5\u201310.","DOI":"10.1109\/VLSIC.1999.797216"},{"key":"14_CR6","unstructured":"J. M. Rabaey, Digital Integrated Circuits, A Design Perspective, Electronics and VLSI Series. Prentice Hall, 1996."},{"key":"14_CR7","doi-asserted-by":"crossref","unstructured":"T. Sakurai and A. R. Newton, \u201cAlpha-Power Law MOSFET Model and its Applications to CMOS Inverter Delay and Other Formulas\u201d, IEEE Journal of Solid-State Circuits, vol. 25, no. 2, pp. 584\u2013594, Apr. 1990.","DOI":"10.1109\/4.52187"}],"container-title":["Lecture Notes in Computer Science","Integrated Circuit Design"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/3-540-45373-3_14","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,2,17]],"date-time":"2019-02-17T00:30:42Z","timestamp":1550363442000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/3-540-45373-3_14"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2000]]},"ISBN":["9783540410683","9783540453734"],"references-count":7,"URL":"https:\/\/doi.org\/10.1007\/3-540-45373-3_14","relation":{},"ISSN":["0302-9743"],"issn-type":[{"type":"print","value":"0302-9743"}],"subject":[],"published":{"date-parts":[[2000]]}}}