{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,1,17]],"date-time":"2025-01-17T05:21:28Z","timestamp":1737091288119,"version":"3.33.0"},"publisher-location":"Berlin, Heidelberg","reference-count":20,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540410683"},{"type":"electronic","value":"9783540453734"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2000]]},"DOI":"10.1007\/3-540-45373-3_17","type":"book-chapter","created":{"date-parts":[[2007,5,28]],"date-time":"2007-05-28T05:29:50Z","timestamp":1180330190000},"page":"168-177","source":"Crossref","is-referenced-by-count":1,"title":["Semi-modular Latch Chains for Asynchronous Circuit Design"],"prefix":"10.1007","author":[{"given":"N.","family":"Starodoubtsev","sequence":"first","affiliation":[]},{"given":"A.","family":"Bystrov","sequence":"additional","affiliation":[]},{"given":"A.","family":"Yakovlev","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2001,9,28]]},"reference":[{"key":"17_CR1","doi-asserted-by":"crossref","unstructured":"M. Kishinevsky, J. Cortadella, A. Kondratyev and L. Lavagno. Asynchronous interfacespecification, analysis and synthesis, Proc. DAC\u201998, pp. 2\u20137.","DOI":"10.1145\/277044.277046"},{"key":"17_CR2","unstructured":"D. E. Muller and W. S. Bartky. A theory of asynchronous circuits. In Proceedings of an International Symposium on the Theory of Switching, pp. 204\u2013243. Harvard University Press, April 1959."},{"key":"17_CR3","doi-asserted-by":"crossref","unstructured":"A. Kondratyev, J. Cortadella, M. Kishinevsky, L. Lavagno, and A. Yakovlev. Logic Decomposition of Speed-Independent Circuits, In Proceedings of the IEEE\/, Vol.87, No.2, February 1999, pp. 347\u2013362.","DOI":"10.1109\/5.740027"},{"issue":"3","key":"17_CR4","first-page":"315","volume":"E80-D","author":"J. Cortadella","year":"1997","unstructured":"J. Cortadella, M. Kishinevsky, A. Kondratyev, L. Lavagno and A. Yakovlev. Petrify: a tool for manipulating concurrent specifications and synthesis of asynchronous controllers, IEICE Trans. Inf. and Syst., Vol. E80-D, No.3, March 1997, pp. 315\u2013325.","journal-title":"IEICE Trans. Inf. and Syst"},{"key":"17_CR5","unstructured":"L.Y. Rosenblum, and A.V. Yakovlev. Signal graphs: From self-timed to timed ones, in Proc. Int. Workshop Timed Petri Nets, Torino, Italy, 1985, pp. 199\u2013207."},{"key":"17_CR6","doi-asserted-by":"crossref","unstructured":"S.B. Furber and J. Liu. Dynamic logic in four-phase micropipelines. Proc. of the Second Int. Symp. on Advanced Research in Asynchronous Circuits and Systems (ASYNC\u201996) March, 1996 Aizu-Wakamatsu, Japan, pp.11\u201316.","DOI":"10.1109\/ASYNC.1996.494433"},{"key":"17_CR7","unstructured":"Steven M. Nowick. Automatic Synthesis of Burst-Mode Asynchronous Controllers. PhD thesis, Stanford University, Department of Computer Science, 1993."},{"key":"17_CR8","unstructured":"Chris J. Myers. Computer-Aided Synthesis and Verification of Gate-Level Timed Circuits. PhD thesis, Dept. of Elec. Eng., Stanford University, October 1995."},{"key":"17_CR9","doi-asserted-by":"crossref","unstructured":"Ken Stevens, Ran Ginosar, and Shai Rotem. Relative timing. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC\u201999), Barcelona, Spain, pages 208\u2013218, April 1999.","DOI":"10.1109\/ASYNC.1999.761535"},{"key":"17_CR10","doi-asserted-by":"crossref","unstructured":"T. Ibaraki, S. Muroga. \u201cSynthesis network with a minimal number of negative gates\u201d, IEEE Trans. on Computers, Vol. C-20. No. 1, January 1971","DOI":"10.1109\/T-C.1971.223081"},{"issue":"10","key":"17_CR11","doi-asserted-by":"publisher","first-page":"928","DOI":"10.1109\/T-C.1973.223620","volume":"C-22","author":"G. Mago","year":"1973","unstructured":"G. Mago, \u201cMonotone function in sequential circuits\u201d, IEEE Trans. on Computers, Vol. C-22. No. 10, October 1973, pp.928\u2013933.","journal-title":"IEEE Trans. on Computers"},{"issue":"2","key":"17_CR12","first-page":"112","volume":"23","author":"N.A. Starodoubtsev","year":"1885","unstructured":"N.A. Starodoubtsev. Asynchronous processes and antitonic control circuits, In: Soviet Journal of Computer and System Science (USA), English translation of Izvestiya Akademii Nauk SSSR. Technicheskaya Kibernetika (USSR), 1885, vol.23, No.2, pp.112\u2013119 (Part I. Description Language), No.6, pp.81-87 (Part II. Basic properties), 1986, Vol.24, No.2, pp.44-51 (part III. Realisation).","journal-title":"Soviet Journal of Computer and System Science (USA)"},{"key":"17_CR13","doi-asserted-by":"crossref","unstructured":"C. Piguet. Logic synthesis of race-free asynchronous sequential circuits. IEEE JSSC, vol.26, No 3, March 1991. pp. 371\u2013380.","DOI":"10.1109\/4.75016"},{"key":"17_CR14","unstructured":"C. Piguet. Synthesis of Asynchronous CMOS Circuits with Negative Gates. Journal of Solid State Devices and Circuits, vol.5, No.2, July 1997."},{"key":"17_CR15","unstructured":"C. Piguet, J. Zahnd. Design of Speed-Independent CMOS Cells from Signal Transition Graphs. PATMOS\u201998. Oct.1998, Copenhagen, pp.357\u2013366."},{"key":"17_CR16","unstructured":"V. Varshavsky (Ed.), Aperiodic Automata, Nauka, Moscow, 1976 (in Russian)."},{"key":"17_CR17","first-page":"289","volume-title":"Switching Theory in Space Technology","author":"D. E. Muller","year":"1963","unstructured":"D. E. Muller. Asynchronous logic and application to information processing, Switching Theory in Space Technology, H. Aiken and W. F. Main, Eds. Stanford, CA; Stanford Univ. Press, 1963, pp. 289\u2013297."},{"key":"17_CR18","doi-asserted-by":"crossref","unstructured":"J. A. Brzozowski and K. Raahemifar. Testing C-elements is not elementary. In Asynchronous Design Methodologies, pp. 150\u2013159. IEEE Computer Society Press, May 1995.","DOI":"10.1109\/WCADM.1995.514652"},{"key":"17_CR19","doi-asserted-by":"crossref","unstructured":"Ivan E. Sutherland. Micropipelines. In: Communications of the ACM. June 1989, vol.32, N6, pp.720\u2013738.","DOI":"10.1145\/63526.63532"},{"key":"17_CR20","unstructured":"M. Josephs. Speed-independent design of a Toggle. Handouts of ACiDWG\/ EXACTWorkshop on Asynchronous Controllers and Interfacing. IMEC, Leuven, Belgium, September 1992."}],"container-title":["Lecture Notes in Computer Science","Integrated Circuit Design"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/3-540-45373-3_17","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,1,16]],"date-time":"2025-01-16T18:35:23Z","timestamp":1737052523000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/3-540-45373-3_17"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2000]]},"ISBN":["9783540410683","9783540453734"],"references-count":20,"URL":"https:\/\/doi.org\/10.1007\/3-540-45373-3_17","relation":{},"ISSN":["0302-9743"],"issn-type":[{"type":"print","value":"0302-9743"}],"subject":[],"published":{"date-parts":[[2000]]}}}