{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,7,15]],"date-time":"2025-07-15T03:33:44Z","timestamp":1752550424026},"publisher-location":"Berlin, Heidelberg","reference-count":11,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540410683"},{"type":"electronic","value":"9783540453734"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2000]]},"DOI":"10.1007\/3-540-45373-3_26","type":"book-chapter","created":{"date-parts":[[2007,5,28]],"date-time":"2007-05-28T05:29:50Z","timestamp":1180330190000},"page":"243-254","source":"Crossref","is-referenced-by-count":14,"title":["Data-Reuse and Parallel Embedded Architectures for Low-Power, Real-Time Multimedia Applications"],"prefix":"10.1007","author":[{"given":"D.","family":"Soudris","sequence":"first","affiliation":[]},{"given":"N. D.","family":"Zervas","sequence":"additional","affiliation":[]},{"given":"A.","family":"Argyriou","sequence":"additional","affiliation":[]},{"given":"M.","family":"Dasygenis","sequence":"additional","affiliation":[]},{"given":"K.","family":"Tatas","sequence":"additional","affiliation":[]},{"given":"C. E.","family":"Goutis","sequence":"additional","affiliation":[]},{"given":"A.","family":"Thanailakis","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2001,9,28]]},"reference":[{"key":"26_CR1","doi-asserted-by":"crossref","DOI":"10.1109\/9780470545058","volume-title":"Low Power Digital CMOS Design","author":"A. P. Chandrakasan","year":"1998","unstructured":"A. P. Chandrakasan, R. W. Brodersen, Low Power Digital CMOS Design, Kluwer Academic Publishers, Boston, 1998."},{"key":"26_CR2","doi-asserted-by":"crossref","DOI":"10.1007\/978-1-4757-2849-1","volume-title":"Custom Memory Management Methodology","author":"F. Catthoor","year":"1998","unstructured":"F. Catthoor, S. Wuytack et al., Custom Memory Management Methodology, Kluwer Academic Publishers, Boston, 1998."},{"issue":"2","key":"26_CR3","doi-asserted-by":"publisher","first-page":"258","DOI":"10.1109\/92.766753","volume":"7","author":"K. Masselos","year":"1999","unstructured":"K. Masselos, F. Catthoor, H. De Man, and C.E. Goutis, and \u201cStrategy for Power Efficient Design of Parallel Systems\u201d, in IEEE Trans. on VLSI, vol. 7, No. 2, June 1999, pp. 258\u2013265.","journal-title":"IEEE Trans. on VLSI"},{"key":"26_CR4","unstructured":"N. D. Zervas, K. Masselos, and C.E. Goutis, \u201cData-reuse exploration for lowpower realization of multimedia applications on embedded cores\u201d, in Proc. of PATMOS\u201999, October 1999, pp. 71\u201380."},{"issue":"1","key":"26_CR5","doi-asserted-by":"publisher","first-page":"14","DOI":"10.1109\/43.739055","volume":"18","author":"U. Eckhardt","year":"1999","unstructured":"U. Eckhardt and R. Merker,\u201cHierarchical Algorithm Partitioning at System Level for an Improved Utilization of Memory Structures\u201d, in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 18, No. 1, January 1999, pp. 14\u201323.","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"26_CR6","doi-asserted-by":"publisher","first-page":"529","DOI":"10.1109\/92.736124","volume":"6","author":"S. Wuytack","year":"1998","unstructured":"S. Wuytack, J.-P. Diguet, F. Catthoor, D. Moolenaar, and H. De Man \u201cFormalized Methodology for Data Reuse Exploration for Low-Power Hierarchical Memory Mappings\u201d, in IEEE Trans. on VLSI Systems, Vol. 6, No. 4, Dec. 1998, pp. 529\u2013537.","journal-title":"IEEE Trans. on VLSI Systems"},{"key":"26_CR7","volume-title":"Journal of VLSI Signal Processing Systems","author":"L. Nachtergaele","year":"1998","unstructured":"L. Nachtergaele, B. Vanhoof, F. Catthoor, D. Moolenaar, and H De Man,\u201cSystemlevel power optimazations of video codecs on embedded cores: a systematic approach\u201d, Journal of VLSI Signal Processing Systems, Kluwer Academic Publishers, Boston, 1998."},{"key":"26_CR8","unstructured":"P. Landman, Low power architectural design methodologies, Doctoral Dissertation, U.C. Berkeley, Aug. 1994."},{"issue":"1","key":"26_CR9","doi-asserted-by":"publisher","first-page":"98","DOI":"10.1109\/4.68123","volume":"SC26","author":"J.M. Mulder","year":"1991","unstructured":"J.M. Mulder, N.T. Quach, and M.J. Flynn,\u201cAn Area Model for On-Chip Memories and its Application\u201d, IEEE Journal of Solid-State Circuits, Vol. SC26, No.1, Feb. 1991, pp.98\u2013105.","journal-title":"IEEE Journal of Solid-State Circuits"},{"key":"26_CR10","volume-title":"Image and Video Compression Standards","author":"V. Bhaskaran","year":"1998","unstructured":"V. Bhaskaran and K. Kostantinides, Image and Video Compression Standards, Kluwer Academic Publishers, Boston, 1998."},{"key":"26_CR11","volume-title":"VLSI Array Processors","author":"S. Y. Kung","year":"1988","unstructured":"S. Y. Kung,\u201cVLSI Array Processors\u201d, Prentice Hall, Eaglewood Cliffs, 1988."}],"container-title":["Lecture Notes in Computer Science","Integrated Circuit Design"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/3-540-45373-3_26","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,2,17]],"date-time":"2019-02-17T00:42:17Z","timestamp":1550364137000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/3-540-45373-3_26"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2000]]},"ISBN":["9783540410683","9783540453734"],"references-count":11,"URL":"https:\/\/doi.org\/10.1007\/3-540-45373-3_26","relation":{},"ISSN":["0302-9743"],"issn-type":[{"type":"print","value":"0302-9743"}],"subject":[],"published":{"date-parts":[[2000]]}}}