{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T21:08:51Z","timestamp":1725484131455},"publisher-location":"Berlin, Heidelberg","reference-count":6,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540410683"},{"type":"electronic","value":"9783540453734"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2000]]},"DOI":"10.1007\/3-540-45373-3_7","type":"book-chapter","created":{"date-parts":[[2007,5,28]],"date-time":"2007-05-28T01:29:50Z","timestamp":1180315790000},"page":"56-65","source":"Crossref","is-referenced-by-count":1,"title":["Framework for High-Level Power Estimation of Signal Processing Architectures"],"prefix":"10.1007","author":[{"given":"Achim","family":"Freimann","sequence":"first","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2001,9,28]]},"reference":[{"issue":"1","key":"7_CR1","doi-asserted-by":"publisher","first-page":"18","DOI":"10.1109\/92.820758","volume":"8","author":"S. Gupta","year":"2000","unstructured":"Gupta, S., Najm, F. N.: Power Modeling for High-Level Power Estimation, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 8, No. 1, (2000) 18\u201329","journal-title":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems"},{"key":"7_CR2","unstructured":"Theoharis, S., Theodoridis, G., Soudris, D., Goutis, C.: Accurate Data Path Models for RT-Level Power Estimation, International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), (1998) 213\u2013222"},{"issue":"2","key":"7_CR3","doi-asserted-by":"publisher","first-page":"173","DOI":"10.1109\/92.386219","volume":"3","author":"P. E. Landman","year":"1995","unstructured":"Landman, P. E., Rabaey, J. M.: Architectual Power Analysis: The Dual Bit Type Method, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 3, No. 2, (1995) 173\u2013187","journal-title":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems"},{"key":"7_CR4","unstructured":"Tsui, C.-Y., Chan, K.-K., Wu, Q. Ding, C.-S., Massoud, P.: A Powerestimation Framework for Designing Low Power Portable Video Applications, Design Automation Conference (DAC), (1997) 421\u2013424"},{"issue":"7","key":"7_CR5","doi-asserted-by":"publisher","first-page":"718","DOI":"10.1109\/43.644033","volume":"16","author":"S. Ramprasad","year":"1997","unstructured":"Ramprasad, S., Shanbhag, N. R., Hajj, I. N.: Analytical Estimation of Signal Transition Activity from Word-Level Statistics, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 16, No. 7, (1997) 718\u2013733","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"7_CR6","unstructured":"Zhang, J., Bergmann, N. W.: A New 8x8 Fast DCT Algorithm for Image Compression, IEEEWorkshop on Visual Signal Processing and Communications, (1993) 57\u201360"}],"container-title":["Lecture Notes in Computer Science","Integrated Circuit Design"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/3-540-45373-3_7","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,2,16]],"date-time":"2019-02-16T19:43:39Z","timestamp":1550346219000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/3-540-45373-3_7"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2000]]},"ISBN":["9783540410683","9783540453734"],"references-count":6,"URL":"https:\/\/doi.org\/10.1007\/3-540-45373-3_7","relation":{},"ISSN":["0302-9743"],"issn-type":[{"type":"print","value":"0302-9743"}],"subject":[],"published":{"date-parts":[[2000]]}}}