{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,9]],"date-time":"2026-06-09T15:34:31Z","timestamp":1781019271746,"version":"3.54.1"},"publisher-location":"Berlin, Heidelberg","reference-count":18,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"value":"9783540429876","type":"print"},{"value":"9783540456827","type":"electronic"}],"license":[{"start":{"date-parts":[[2001,1,1]],"date-time":"2001-01-01T00:00:00Z","timestamp":978307200000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2001]]},"DOI":"10.1007\/3-540-45682-1_15","type":"book-chapter","created":{"date-parts":[[2007,5,26]],"date-time":"2007-05-26T06:31:48Z","timestamp":1180161108000},"page":"239-254","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":312,"title":["A Compact Rijndael Hardware Architecture with S-Box Optimization"],"prefix":"10.1007","author":[{"given":"Akashi","family":"Satoh","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Sumio","family":"Morioka","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Kohji","family":"Takano","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Seiji","family":"Munetoh","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"297","published-online":{"date-parts":[[2001,11,20]]},"reference":[{"key":"15_CR1","unstructured":"ANSI (American National Standards Institute). Triple Data Encryption Algorithm Modes of Operation, 1998."},{"key":"15_CR2","unstructured":"J. Daemen and V. Rijmen. AES Proposal: Rijndael. NIST AES Proposal, June 1998. Available at http:\/\/csrc.nist.gov\/encryption\/aes \/rijndael\/Rijndael.pdf ."},{"key":"15_CR3","unstructured":"A. J. Elbirt, W. Yip, B. Chetwynd, and C. Paar. An FPGA Implementation and Performance Evaluation of the AES Block Cipher Candidate Algorithm Finalists. In The Third Advanced Encryption Standard Candidate Conference, pages 13\u201327. NIST, April 2000. Available at http:\/\/csrc.nist.gov\/encryption\/aes\/round2\/conf3\/papers\/08-aelbirt.pdf ."},{"key":"15_CR4","doi-asserted-by":"crossref","unstructured":"J.L. Fan and C. Paar. On Efficient Inversion in Tower Fields of Characteristic Two. In International Symposium on Information Theory, page 20. IEEE, June 1997.","DOI":"10.1109\/ISIT.1997.612935"},{"key":"15_CR5","doi-asserted-by":"crossref","unstructured":"V. Fischer and M. Drutarovsky. Two Methods of Rijndael Implementation in Reconfigurable Hardware. In Workshop on Cryptographic Hardware and Embedded Systems (CHES2001), pages 81\u201396, May 2001.","DOI":"10.1007\/3-540-44709-1_8"},{"key":"15_CR6","unstructured":"K. Gaj and P. Chodowiec. Comparison of the Hardware Prformance of the AES Candidates using Reconfigurable Hardware. In The Third Advanced Encryption Standard Candidate Conference, pages 40\u201356. NIST, April 2000. Available at http:\/\/csrc.nist.gov\/encryption\/aes\/round2\/conf3\/papers\/22-kgaj.pdf ."},{"key":"15_CR7","series-title":"Lect Notes Comput Sci","doi-asserted-by":"publisher","first-page":"342","DOI":"10.1007\/BFb0052247","volume-title":"Advances in Cryptology\u2014CRYPTO\u2019 97","author":"J. Guajardo","year":"1997","unstructured":"J. Guajardo and C. Paar. Efficient Algorithms for Elliptic Curve Cryptosystems. In Jr. Burton S. Kaliski, editor, Advances in Cryptology\u2014CRYPTO\u2019 97, volume 1294 of Lecture Notes in Computer Science, pages 342\u2013356. Springer-Verlag, August 1997."},{"key":"15_CR8","unstructured":"T. Ichikawa, T. Kasuya, and M. Matsui. Hardware Evaluation of the AES Finalists. In The Third Advanced Encryption Standard Candidate Conference, pages 279\u2013285. NIST, April 2000. Available at http:\/\/csrc.nist.gov\/encryption\/aes\/round2\/conf3\/papers\/15-tichikawa.pdf ."},{"key":"15_CR9","unstructured":"T. Ichikawa, T. Tokita, and M. Matsui. On Hardware Implementation of 128-bit Block Ciphers (III). In 2001 Symposium on Cryptography and Information Security (SCIS 2001), pages 669\u2013674, January 2001. (Japanese)."},{"key":"15_CR10","doi-asserted-by":"crossref","unstructured":"H. Kuo and I. Verbauwhede. Architectural Optimization for a 1.82 Gbits\/sec VLSI Implementation of the AES Rijndael Algorithm. In Workshop on Cryptographic Hardware and Embedded Systems (CHES2001), pages 53\u201367, May 2001.","DOI":"10.1007\/3-540-44709-1_6"},{"key":"15_CR11","doi-asserted-by":"crossref","unstructured":"M. McLoone and J.V. McCanny. High performance Single-chip FPGA Rijndael Algorithm Implementations. In Workshop on Cryptographic Hardware and Embedded Systems (CHES2001), pages 68\u201380, May 2001.","DOI":"10.1007\/3-540-44709-1_7"},{"key":"15_CR12","doi-asserted-by":"crossref","unstructured":"S. Morioka and Y. Katayama. Design Methodology for a One-Shot Reed-Solomon Encoder and Decoder. In International Conference on Computer Design (ICCD\u2019 99), pages 60\u201367. IEEE, October 1999.","DOI":"10.1109\/ICCD.1999.808384"},{"key":"15_CR13","unstructured":"National Institute of Standards and Technology (U.S.). Advanced Encryption Standard (AES). Available at http:\/\/csrc.nist.gov\/publications\/drafts\/d.ps-AES.pdf ."},{"key":"15_CR14","unstructured":"National Institute of Standards and Technology (U.S.). Data Encryption Standard (DES). FIPS Publication 46-3, NIST, 1999. Available at http:\/\/csrc.nist.gov\/publications\/.ps\/.ps46-3\/.ps46-3.pdf ."},{"issue":"7","key":"15_CR15","doi-asserted-by":"publisher","first-page":"856","DOI":"10.1109\/12.508323","volume":"45","author":"C. Paar","year":"1996","unstructured":"C. Paar. A New Architecture for a Parallel Finite Field Multiplier with Low Complexity Based on Composite Fields. IEEE Transactions on Computers, 45(7):856\u2013861, July 1996.","journal-title":"IEEE Transactions on Computers"},{"key":"15_CR16","doi-asserted-by":"crossref","unstructured":"A. Rudra, P.K. Dubey, C.S. Jutla, V. Kumar, J.R. Rao, and P. Rohatgi. Efficient Rijndael Encryption Implementation with Composite Field Arithmetic. In Workshop on Cryptographic Hardware and Embedded Systems (CHES2001), pages 175\u2013188, May 2001.","DOI":"10.1007\/3-540-44709-1_16"},{"key":"15_CR17","unstructured":"N. Weaver and J. Wawrzynek. A Comparison of the AES Candidates Amenability to FPGA Implementation. In The Third Advanced Encryption Standard Candidate Conference, pages 28\u201339. NIST, April 2000. Available at http:\/\/csrc.nist.gov\/encryption\/aes\/round2\/conf3\/papers\/13-nweaver.pdf ."},{"key":"15_CR18","unstructured":"B. Weeks, M. Bean, T. Rozylowicz, and C. Ficke. Hardware Performance Simulation of Round 2 Advanced Encryption Standard Algorithm. Available at http:\/\/csrc.nist.gov \/encryption\/aes\/round2\/NSA-AES.nalreport.pdf ."}],"container-title":["Lecture Notes in Computer Science","Advances in Cryptology \u2014 ASIACRYPT 2001"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/3-540-45682-1_15","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,1,16]],"date-time":"2025-01-16T18:12:39Z","timestamp":1737051159000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/3-540-45682-1_15"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2001]]},"ISBN":["9783540429876","9783540456827"],"references-count":18,"URL":"https:\/\/doi.org\/10.1007\/3-540-45682-1_15","relation":{},"ISSN":["0302-9743"],"issn-type":[{"value":"0302-9743","type":"print"}],"subject":[],"published":{"date-parts":[[2001]]},"assertion":[{"value":"20 November 2001","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}}]}}