{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,1,22]],"date-time":"2025-01-22T11:40:04Z","timestamp":1737546004294,"version":"3.33.0"},"publisher-location":"Berlin, Heidelberg","reference-count":23,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540440499"},{"type":"electronic","value":"9783540457060"}],"license":[{"start":{"date-parts":[[2002,1,1]],"date-time":"2002-01-01T00:00:00Z","timestamp":1009843200000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2002]]},"DOI":"10.1007\/3-540-45706-2_68","type":"book-chapter","created":{"date-parts":[[2007,10,7]],"date-time":"2007-10-07T05:37:18Z","timestamp":1191735438000},"page":"500-511","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["A Register File Architecture and Compilation Scheme for Clustered ILP Processors"],"prefix":"10.1007","author":[{"given":"Krishnan","family":"Kailas","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Manoj","family":"Franklin","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kemal","family":"Ebcio\u011flu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2002,8,20]]},"reference":[{"key":"68_CR1","doi-asserted-by":"crossref","unstructured":"V. Zyuban and P. M. Kogge, \u201cInherently Lower-Power High-Performance Superscalar Architectures,\u201d IEEE Trans. on Computers, vol. 50, pp. 268\u2013285, Mar. 2001.","DOI":"10.1109\/12.910816"},{"key":"68_CR2","doi-asserted-by":"crossref","unstructured":"P. Faraboschi, J. Fisher, G. Brown, G. Desoli, and F. Homewood, \u201cLx: A Technology Platform for Customizable VLIW Embedded Processing,\u201d in Proceedings of the 27th International Symposium on Computer Architecture, June 2000.","DOI":"10.1145\/339647.339682"},{"key":"68_CR3","doi-asserted-by":"crossref","unstructured":"K. Ebcio\u011flu, J. Fritts, S. Kosonocky, M. Gschwind, E. Altman, K. Kailas, and T. Bright, \u201cAn Eight-Issue Tree-VLIW Processor for Dynamic Binary Translation,\u201d in Proc. of Int. Conf. on Computer Design (ICCD\u201998), pp. 488\u2013495, 1998.","DOI":"10.1109\/ICCD.1998.727094"},{"key":"68_CR4","unstructured":"Texas Instruments, Inc., TMS320C62x\/C67x Technical Brief Apr. 1998."},{"key":"68_CR5","doi-asserted-by":"crossref","unstructured":"J. Fridman and Z. Greenfield, \u201cThe TigerSHARC DSP architecture,\u201d IEEE Micro, vol. 20, pp. 66\u201376, Jan.\/Feb. 2000.","DOI":"10.1109\/40.820055"},{"key":"68_CR6","doi-asserted-by":"crossref","unstructured":"R. E. Kessler, \u201cThe Alpha 21264 microprocessor,\u201d IEEE Micro, vol. 19, pp. 24\u201336, Mar.\/Apr. 1999.","DOI":"10.1109\/40.755465"},{"key":"68_CR7","doi-asserted-by":"crossref","unstructured":"R. Canal, J. M. Parcerisa, and A. Gonzalez, \u201cDynamic cluster assignment mech-anisms,\u201d in Proc. of the 6th Int. Conference on High-Performance Computer Architecture (HPCA-6), pp. 133\u2013142, Jan. 2000.","DOI":"10.1109\/HPCA.2000.824345"},{"key":"68_CR8","unstructured":"K. Kailas, Microarchitecture and Compilation Support for Clustered ILP Processors. PhD thesis, Dept. of ECE, University of Maryland, College Park, Mar 2001."},{"key":"68_CR9","doi-asserted-by":"crossref","unstructured":"R. P. Colwell et al., \u201cA VLIW architecture for a trace scheduling compiler,\u201d IEEE Transactions on Computers, vol. C-37, pp. 967\u2013979, Aug. 1988.","DOI":"10.1109\/12.2247"},{"key":"68_CR10","doi-asserted-by":"crossref","unstructured":"S. Keckler, W. Dally, D. Maskit, N. Carter, A. Chang, and W. Lee, \u201cExploiting fine-grain thread level parallelism on the MIT Multi-ALU processor,\u201d in Proc. of the 25th Annual Int. Symposium on Computer Architecture, pp. 306\u2013317, 1998.","DOI":"10.1145\/279361.279399"},{"key":"68_CR11","doi-asserted-by":"crossref","unstructured":"A. Capitanio, N. Dutt, and A. Nicolau, \u201cPartitioned register files for VLIWs: A preliminary analysis of tradeoffs,\u201d in Proceedings of the 25th Annual International Symposium on Microarchitecture, pp. 292\u2013300, Dec. 1-4, 1992.","DOI":"10.1145\/144965.145839"},{"key":"68_CR12","doi-asserted-by":"crossref","unstructured":"K. Kailas, K. Ebcio\u011flu, and A. Agrawala, \u201ccars: A New Code Generation Framework for Clustered ILP Processors,\u201d in Proceedings of the 7th International Symposium on High-Performance Computer Architecture (HPCA-7), pp. 133\u2013143, 2001.","DOI":"10.1109\/HPCA.2001.903258"},{"key":"68_CR13","doi-asserted-by":"crossref","unstructured":"K. Pingali, M. Beck, R. Johnson, M. Moudgill, and P. Stodghill, \u201cDependence flow graphs: an algebraic approach to program dependencies,\u201d in Proc. of the 18th annual ACM symposium on Principles of programming languages, pp. 67\u201378, 1991.","DOI":"10.1145\/99583.99595"},{"key":"68_CR14","volume-title":"ch. 2. Computer and job-shop scheduling theory","author":"R. Sethi","year":"1976","unstructured":"R. Sethi, Algorithms for minimal-length schedules, ch. 2. Computer and job-shop scheduling theory (E. G. Coffman, ed.), John Wiley & Sons, Inc., New York., 1976."},{"key":"68_CR15","unstructured":"M. Moudgill, \u201cImplementing an Experimental VLIW Compiler,\u201d IEEE Technical Committee on Computer Architecture Newsletter, pp. 39\u201340, June 1997."},{"key":"68_CR16","unstructured":"P. R. Nuth, The Named-State Register File. PhD thesis, MIT, AI Lab, Aug. 1993."},{"key":"68_CR17","unstructured":"H. H. J. Hum, K. B. Theobald, and G. R. Gao, \u201cBuilding multithreaded architectures with off-the-shelf microprocessors,\u201d in Proceedings of the 8th International Symposium on Parallel Processing, pp. 288\u2013297, 1994."},{"key":"68_CR18","unstructured":"E. H. Jensen, \u201cPipelined register cache.\u201d U.S. Patent No. 5,117,493, May 1992."},{"key":"68_CR19","doi-asserted-by":"crossref","unstructured":"R. Yung and N. C. Wilhelm, \u201cCaching processor general registers,\u201d in International Conference on Computer Design, pp. 307\u2013312, 1995.","DOI":"10.1109\/ICCD.1995.528826"},{"key":"68_CR20","unstructured":"M. M. Fernandes, J. Llosa, and N. Topham, \u201cExtending a VLIW Architecture Model,\u201d technical report ECS-CSG-34-97, Dept. of CS, Edinburgh University, 1997."},{"key":"68_CR21","doi-asserted-by":"crossref","unstructured":"J. Llosa, M. Valero, and E. Ayguade, \u201cNon-consistent dual register files to reduce register pressure,\u201d in Proceedings of the First International Symposium on High-Performance Computer Architecture, pp. 22\u201331, 1995.","DOI":"10.1109\/HPCA.1995.386558"},{"key":"68_CR22","doi-asserted-by":"crossref","unstructured":"J.-L. Cruz, A. Gonz\u00e1lez, M. Valero, and N. P. Topham, \u201cMultiple-banked register file architectures,\u201d in Proceedings of the 27th Annual International Symposium on Computer Architecture, pp. 316\u2013325, 2000.","DOI":"10.1145\/342001.339708"},{"key":"68_CR23","doi-asserted-by":"crossref","unstructured":"J. Zalamea, J. Llosa, E. Ayguade, and M. Valero, \u201cTwo-level hierarchical register file organization for VLIW processors,\u201d in Proceedings of the 33rd Annual International Symposium on Microarchitecture (MICRO-33), 2000.","DOI":"10.1145\/360128.360143"}],"container-title":["Lecture Notes in Computer Science","Euro-Par 2002 Parallel Processing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/3-540-45706-2_68","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,1,21]],"date-time":"2025-01-21T12:43:59Z","timestamp":1737463439000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/3-540-45706-2_68"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2002]]},"ISBN":["9783540440499","9783540457060"],"references-count":23,"URL":"https:\/\/doi.org\/10.1007\/3-540-45706-2_68","relation":{},"ISSN":["0302-9743"],"issn-type":[{"type":"print","value":"0302-9743"}],"subject":[],"published":{"date-parts":[[2002]]},"assertion":[{"value":"20 August 2002","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}},{"value":"This content has been made available to all.","name":"free","label":"Free to read"}]}}