{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,10]],"date-time":"2026-03-10T13:10:16Z","timestamp":1773148216788,"version":"3.50.1"},"publisher-location":"Berlin, Heidelberg","reference-count":7,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"value":"9783540441434","type":"print"},{"value":"9783540457169","type":"electronic"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2002]]},"DOI":"10.1007\/3-540-45716-x_18","type":"book-chapter","created":{"date-parts":[[2007,8,2]],"date-time":"2007-08-02T15:57:08Z","timestamp":1186070228000},"page":"178-187","source":"Crossref","is-referenced-by-count":2,"title":["PA-ZSA (Power-Aware Zero-Slack Algorithm): A Graph-Based Timing Analysis for Ultra-Low Power CMOS VLSI"],"prefix":"10.1007","author":[{"given":"Kyu-won","family":"Choi","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Abhijit","family":"Chatterjee","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2002,8,27]]},"reference":[{"key":"18_CR1","doi-asserted-by":"crossref","unstructured":"A. Chandrakasan, S. Sheng, and R. Brodersen, \u201cLow-power CMOS digital design,\u201d IEEE Journal of Solid-State Circuits, vol. 27, pp. 473\u2013484, April 1992.","DOI":"10.1109\/4.126534"},{"key":"18_CR2","doi-asserted-by":"crossref","unstructured":"J.M. Rabaey and M. Pedram, Low Power Design Methodologies, Kluwer Academic Publishers, 1996, pp 21\u201364, 130-160.","DOI":"10.1007\/978-1-4615-2307-9"},{"key":"18_CR3","doi-asserted-by":"crossref","unstructured":"R. Nair, C.L. Berman, P.S. hauge, and E.J. Yoffe, \u201cGeneration of performance constraints for layout,\u201d IEEE Transactions on Computer-Aided Design, pp.860\u2013874, Aug. 1989.","DOI":"10.1109\/43.31546"},{"key":"18_CR4","doi-asserted-by":"crossref","unstructured":"T. Gao, P.M. Vaidya, and C.L. Liu,\u201dA new performance driven placement algorithm,\u201d Proc. of ICCAD, pp. 44\u201347, 1991.","DOI":"10.1109\/ICCAD.1991.185187"},{"key":"18_CR5","doi-asserted-by":"crossref","unstructured":"H. Youssef and E. Shragowitz, \u201cTiming constraints for correct performance,\u201d Proc. of ICCAD, pp. 24\u201327, 1990.","DOI":"10.1109\/ICCAD.1990.129830"},{"key":"18_CR6","unstructured":"C. Chen, X. Yang, and M. Sarrafzadeh, \u201cPotential slack: an effective metric of combinational circuit performance,\u201d Proc. of ICCAD, pp. 198\u2013201, 2000."},{"issue":"4","key":"18_CR7","doi-asserted-by":"publisher","first-page":"538","DOI":"10.1109\/92.736125","volume":"6","author":"P. Pant","year":"1998","unstructured":"P. Pant, V. De, and A. Chatterjee, \u201cSimultaneous power Supply, threshold voltage, and transistor size optimization for low-power operation of CMOS circuits,\u201d IEEE Trans. On VLSI Systems, vol. 6, no. 4, pp. 538\u2013545, December 1998.","journal-title":"IEEE Trans. On VLSI Systems"}],"container-title":["Lecture Notes in Computer Science","Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/3-540-45716-X_18","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,5,1]],"date-time":"2019-05-01T18:08:11Z","timestamp":1556734091000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/3-540-45716-X_18"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2002]]},"ISBN":["9783540441434","9783540457169"],"references-count":7,"URL":"https:\/\/doi.org\/10.1007\/3-540-45716-x_18","relation":{},"ISSN":["0302-9743"],"issn-type":[{"value":"0302-9743","type":"print"}],"subject":[],"published":{"date-parts":[[2002]]}}}