{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T22:19:30Z","timestamp":1725488370288},"publisher-location":"Berlin, Heidelberg","reference-count":14,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540441434"},{"type":"electronic","value":"9783540457169"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2002]]},"DOI":"10.1007\/3-540-45716-x_23","type":"book-chapter","created":{"date-parts":[[2007,8,2]],"date-time":"2007-08-02T11:57:08Z","timestamp":1186055828000},"page":"229-238","source":"Crossref","is-referenced-by-count":1,"title":["Output Waveform Evaluation of Basic Pass Transistor Structure"],"prefix":"10.1007","author":[{"given":"S.","family":"Nikolaidis","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"H.","family":"Pournara","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"A.","family":"Chatzigeorgiou","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2002,8,27]]},"reference":[{"key":"23_CR1","doi-asserted-by":"publisher","first-page":"1079","DOI":"10.1109\/4.597298","volume":"32","author":"R. Zimmermann","year":"1997","unstructured":"Zimmermann R. and Fichtner W.: Low-Power Logic Styles: CMOS Versus Pass-Transistor Logic, IEEE J. Solid-State Circuits, Vol. 32, (1997), 1079\u20131090","journal-title":"IEEE J. Solid-State Circuits"},{"key":"23_CR2","doi-asserted-by":"publisher","first-page":"1145","DOI":"10.1109\/4.245595","volume":"28","author":"M. Suzuki","year":"1993","unstructured":"Suzuki M., Ohkubo N., Shinbo T., Yamanaka T., Shimizu A., Sasaki K. and Nakagome Y.: A 1.5-ns 32-b CMOS ALU in Double Pass-Transistor Logic, IEEE J. Solid-State Circuits, vol. 28, (1993), 1145\u20131150","journal-title":"IEEE J. Solid-State Circuits"},{"key":"23_CR3","doi-asserted-by":"publisher","first-page":"1535","DOI":"10.1109\/4.540066","volume":"31","author":"I.S. Abu-Khater","year":"1996","unstructured":"Abu-Khater I.S., Bellaouar A., Elmasry M. I.: Circuit Techniques for CMOS Low-Power High-Performance Multipliers, IEEE J. Solid-State Circuits, vol. 31, (1996), 1535\u20131546","journal-title":"IEEE J. Solid-State Circuits"},{"key":"23_CR4","doi-asserted-by":"publisher","first-page":"792","DOI":"10.1109\/4.509865","volume":"31","author":"K. Yano","year":"1996","unstructured":"Yano K., Sasaki Y., Rikino K. and Seki K.: Top-Down Pass-Transistor Logic Design, IEEE J. Solid-State Circuits, vol. 31, (1996) 792\u2013803","journal-title":"IEEE J. Solid-State Circuits"},{"key":"23_CR5","doi-asserted-by":"publisher","first-page":"584","DOI":"10.1109\/4.52187","volume":"25","author":"T. Sakurai","year":"1990","unstructured":"Sakurai T., Newton A.R: Alpha-Power Law MOSFET Model and its Applications to CMOS Inverter Delay and Other Formulas, IEEE J. Solid-State Circuits, Vol. 25, (1990), 584\u2013594","journal-title":"IEEE J. Solid-State Circuits"},{"key":"23_CR6","unstructured":"Juan-Chico J., Bellido M. J., Acosta A. J., Barriga A., Valencia M.: Delay degradation effect in submicronic CMOS inverters, Proc. of 7th Int. Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), (1997), 215\u2013224"},{"issue":"2","key":"23_CR7","doi-asserted-by":"publisher","first-page":"302","DOI":"10.1109\/4.658636","volume":"33","author":"L. Bisdounis","year":"1998","unstructured":"L. Bisdounis, S. Nikolaidis, O. Koufopavlou, \u226aAnalytical Transient Response and Propagation Delay Evaluation of the CMOS Inverter for Short-channel Devices\u226b, IEEE Journal of Solid-State Circuits, Vol. 33, No 2, pp. 302\u2013306, Feb. 1998.","journal-title":"IEEE Journal of Solid-State Circuits"},{"key":"23_CR8","doi-asserted-by":"publisher","first-page":"42","DOI":"10.1109\/4.736655","volume":"34","author":"J. M. Daga","year":"1999","unstructured":"Daga J. M. and Auvergne D.: A Comprehensive Delay Macro Modeling for Submicrometer CMOS Logics, IEEE J. Solid-State Circuits, Vol. (34), (1999), 42\u201355","journal-title":"IEEE J. Solid-State Circuits"},{"key":"23_CR9","doi-asserted-by":"publisher","first-page":"557","DOI":"10.1109\/43.759070","volume":"18","author":"A. Chatzigeorgiou","year":"1999","unstructured":"Chatzigeorgiou A., Nikolaidis S. and Tsoukalas I.: A Modeling Technique for CMOS Gates, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 18, (1999), 557\u2013575","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"23_CR10","doi-asserted-by":"publisher","first-page":"433","DOI":"10.1109\/43.992767","volume":"21","author":"J. L. Rossello","year":"2002","unstructured":"Rossello J. L. and Segura J.: Charge-Based Analytical Model for the Evaluation of Power Consumption in Submicron CMOS Buffers, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 21, (2002), 433\u2013448","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"23_CR11","doi-asserted-by":"crossref","first-page":"90","DOI":"10.1080\/02286203.1995.11760258","volume":"15","author":"S. R. Vemuru","year":"1995","unstructured":"Vemuru S. R.: Delay-Macromodelling of CMOS Transmission-Gate-Based-Circuits, International Journal of Modelling and Simulation, vol. 15, (1995), 90\u201397","journal-title":"International Journal of Modelling and Simulation"},{"key":"23_CR12","unstructured":"Kang S. M. and Leblebici Y.: CMOS Digital Integrated Circuits, Analysis and Design, McGraw Hill, New York (1996)"},{"key":"23_CR13","unstructured":"Chatzigeorgiou A., Nikolaidis S. and I. Tsoukalas I.: Timing Analysis of Pass Transistor and CPL Gates, Proc. of 9th Int. Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), (1999), 367\u2013376"},{"key":"23_CR14","volume-title":"Principles of CMOS VLSI Design","author":"N. H. E. Weste","year":"1994","unstructured":"Weste N. H. E. and Eshraghian K., Principles of CMOS VLSI Design, Addison Wesley, Reading (1994)"}],"container-title":["Lecture Notes in Computer Science","Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/3-540-45716-X_23","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,2,17]],"date-time":"2019-02-17T16:36:06Z","timestamp":1550421366000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/3-540-45716-X_23"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2002]]},"ISBN":["9783540441434","9783540457169"],"references-count":14,"URL":"https:\/\/doi.org\/10.1007\/3-540-45716-x_23","relation":{},"ISSN":["0302-9743"],"issn-type":[{"type":"print","value":"0302-9743"}],"subject":[],"published":{"date-parts":[[2002]]}}}