{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,9,26]],"date-time":"2026-09-26T14:36:24Z","timestamp":1790433384437,"version":"4.1.0"},"publisher-location":"Berlin, Heidelberg","reference-count":20,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"value":"9783540441434","type":"print"},{"value":"9783540457169","type":"electronic"}],"license":[{"start":{"date-parts":[[2002,1,1]],"date-time":"2002-01-01T00:00:00Z","timestamp":1009843200000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2002]]},"DOI":"10.1007\/3-540-45716-x_39","type":"book-chapter","created":{"date-parts":[[2007,8,2]],"date-time":"2007-08-02T15:57:08Z","timestamp":1186070228000},"page":"390-399","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":5,"title":["Dynamic Voltage Scheduling for Real Time Asynchronous Systems"],"prefix":"10.1007","author":[{"given":"Mohammed Es","family":"Salhiene","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Laurent","family":"Fesquet","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Marc","family":"Renaudin","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"297","published-online":{"date-parts":[[2002,8,27]]},"reference":[{"key":"39_CR1","first-page":"73","volume":"36","author":"M. Pedram","year":"1997","unstructured":"Pedram, M.: Design Technologies for Low Power VLSI. In: Encyclopedia of Computer Science and Technology, Vol. 36. Marcel Dekker, Inc., (1997) 73\u201396","journal-title":"Encyclopedia of Computer Science and Technology"},{"issue":"3","key":"39_CR2","doi-asserted-by":"publisher","first-page":"299","DOI":"10.1109\/92.845896","volume":"8","author":"L. Benini","year":"2000","unstructured":"Benini, L., Bogliolo, A., De Micheli, G.: A Survey of Design Techniques for System-Level Dynamic Power Management. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 8, N\u00b0 3, (June 2000) 299\u2013316","journal-title":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems"},{"key":"39_CR3","unstructured":"Mudge, T.: Power: A First-Class Architectural Design Constraint. IEEE Computer, (2001) 52\u201358"},{"key":"39_CR4","unstructured":"Gowan, M.K., Biro, L.L., Jackson, D.B.: Power Considerations in the Design of the Alpha 21264 Microprocessor. 35th Design Automation Conference, San Francisco, CA USA (1998) 726\u2013731"},{"key":"39_CR5","doi-asserted-by":"crossref","unstructured":"Nielsen, L.S., Niessen, C., Sparso, J., Van Berkel, J.: Low Power Operation Using Self-Timed Circuits and Adaptative Scaling of the Supply Voltage. In: IEEE Transaction on Very large Scale Integration (VLSI) Systems, Vol. 2, N\u00b04, (December 1994)","DOI":"10.1109\/92.335008"},{"issue":"4","key":"39_CR6","doi-asserted-by":"publisher","first-page":"473","DOI":"10.1109\/4.126534","volume":"27","author":"A.P. Chandrakasan","year":"1992","unstructured":"Chandrakasan, A.P., Sheng, S., Brodersen, R.W.: Low Power CMOS Digital Design. In: IEEE Journal of Solid-State Circuits, Vol. 27, N\u00b0 4, (April 1992) 473\u2013484","journal-title":"IEEE Journal of Solid-State Circuits"},{"key":"39_CR7","doi-asserted-by":"crossref","unstructured":"Burd, T., Brodersen, R.W.: Energy Efficient CMOS Microprocessor Design. Proc. 28th Hawa\u00ef Int\u2019l Cof. on System Sciences, Vol. 1, (Jan 1995) 288\u2013297","DOI":"10.1109\/HICSS.1995.375385"},{"key":"39_CR8","unstructured":"Smit, G.J.M., Havinga, P.J.M.: A survey of energy saving techniques for mobile computers. Moby Dick technical report (1997) http:\/\/www.cs.utwente.nl\/~havinga\/papers\/energy.ps"},{"key":"39_CR9","doi-asserted-by":"crossref","unstructured":"Simunic, T., Benini, L., Acquaviva, A., De Micheli, G.: Dynamic Voltage Scaling for Portable Systems. 38th Design Automation Conference, Las Vegas (18\u201322 June 2001) 524\u2013529","DOI":"10.1145\/378239.379016"},{"key":"39_CR10","unstructured":"Lu, Y.H., Benini, L., De Micheli, G.: Operating-System Directed Power Reduction. ISLPED\u201900, Rapallo, Italy (2000) 37\u201342"},{"key":"39_CR11","unstructured":"Lu, Y.H., De Micheli, G.: Comparing System-Level Power Management Policies. IEEE Design & test of Computers, (2001) 10\u201319"},{"issue":"1","key":"39_CR12","doi-asserted-by":"publisher","first-page":"42","DOI":"10.1109\/92.486080","volume":"4","author":"M.B. Srivasta","year":"1996","unstructured":"Srivasta, M.B., Chandrakasan, A.P., Brodersen, R.W.: Predictive System Shutdown and Other Architectural Techniques for Energy Effcicient Programmable Computation. IEEE Transactions on very Large Scale Integration (VLSI) Systems, Vol. 4, N\u00b01, (March 1996) 42\u201355","journal-title":"IEEE Transactions on very Large Scale Integration (VLSI) Systems"},{"key":"39_CR13","unstructured":"Flautner, K.: Automatic Monitoring for Interactive Performance and Power Reduction. Dissertation, Michigan University (2001)"},{"key":"39_CR14","unstructured":"Pering, T., Burd, T., Broderesen, R.: Dynamic Voltage Scaling and the Design of a Low-Power Microprocessor System. In: Power-Driven Microarchitecture Workshop, in conjunction with Intl. Symposium on Computer Architecture, Barcelona, Spain, (June 1998)"},{"key":"39_CR15","unstructured":"Weiser, M., Welch, B., Demers, A., Shenker, S.: Scheduling for reduced CPU energy. In: USENIX Symposium on Operating Systems Design and Implementation, (1994) 13\u201325"},{"key":"39_CR16","unstructured":"Govil, K., Chan, E., Wassermann, H.: Comparing algorithms for dynamic speed-setting of a low-power CPU. In: ACM International Conference on Mobile Computing and Networking, (1995) 13\u201325"},{"key":"39_CR17","unstructured":"Pering, T., Burd, T., Brodersen, R.: Voltage Scheduling in the lpARM Microprocessor System. ISLPED\u2019 00, Rapallo, Italy (2000) 96\u2013101"},{"key":"39_CR18","unstructured":"Kumar, P., Srivastava, M.: Predictive Strategies for Low-Power RTOS Scheduling. IEEE (2000) 343\u2013348"},{"key":"39_CR19","unstructured":"Renaudin, M., Vivet, P., Robin, F.: ASPRO: an Asynchronous 16-Bit RISC Microprocessor with DSP Capabilities. ESSCIRC 99, Duisburg, Germany, (21\u201323 Sept.1999) 28\u201331"},{"key":"39_CR20","unstructured":"Renaudin, M., Vivet, P., Robin, F.: ASPRO-216: a standard-cell Q.D.I. 16-bit RISC asynchronous microprocessor. Proc. of the Fourth International Symposium on Advanced Research in Asynchronous Circuits and Systems, IEEE (1998) 22\u201323"}],"container-title":["Lecture Notes in Computer Science","Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/3-540-45716-X_39","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,1,20]],"date-time":"2025-01-20T02:53:10Z","timestamp":1737341590000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/3-540-45716-X_39"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2002]]},"ISBN":["9783540441434","9783540457169"],"references-count":20,"URL":"https:\/\/doi.org\/10.1007\/3-540-45716-x_39","relation":{},"ISSN":["0302-9743"],"issn-type":[{"value":"0302-9743","type":"print"}],"subject":[],"published":{"date-parts":[[2002]]},"assertion":[{"value":"27 August 2002","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}}]}}