{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T22:19:13Z","timestamp":1725488353360},"publisher-location":"Berlin, Heidelberg","reference-count":6,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540441434"},{"type":"electronic","value":"9783540457169"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2002]]},"DOI":"10.1007\/3-540-45716-x_4","type":"book-chapter","created":{"date-parts":[[2007,8,2]],"date-time":"2007-08-02T15:57:08Z","timestamp":1186070228000},"page":"35-44","source":"Crossref","is-referenced-by-count":0,"title":["MDSP: A High-Performance Low-Power DSP Architecture"],"prefix":"10.1007","author":[{"given":"F.","family":"Pessolano","sequence":"first","affiliation":[]},{"given":"J.","family":"Kessels","sequence":"additional","affiliation":[]},{"given":"A.","family":"Peeters","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2002,8,27]]},"reference":[{"key":"4_CR1","doi-asserted-by":"crossref","unstructured":"Faraboschi P., et al., The latest word in digital and media processing, IEEE Signal Processing Magazine, 59\u201385, March 1998","DOI":"10.1109\/79.664698"},{"key":"4_CR2","doi-asserted-by":"crossref","unstructured":"Van Eijndhoven J.T.J., et al., TriMedia CPU64 Architecture, Proc. Of the Intl. Conference on Computer Design, Austin, Oct. 1999","DOI":"10.1109\/ICCD.1999.808601"},{"key":"4_CR3","unstructured":"Scott J., et al., Designing the M\n                           *\n                           CORE M3 CPU Architecture, Proc. Of the Intl. Conference on Computer Design, Austin, Oct. 1999"},{"key":"4_CR4","unstructured":"Lambers E., et al., R.E.A.L. DSP: Reconfigurable Embedded DSP Architecture for Low-Power\/Low-Cost Telecom Baseband Processing, 1st IEEE Workshop on Circuit and Systems for Wireless Communication, Lucerne, 1998"},{"key":"4_CR5","unstructured":"Pessolano, F. et al., Towards a high-performance asynchronous-friendly DSP architectural template, 4th AciD Workshop on Asynchronous Circuits and Systems, France, 2000"},{"key":"4_CR6","unstructured":"Van Gageldonk H., An Asynchronous Low-power 80C51 Microcontroller, Ph.D. Thesis, Technical University of Eindhoven, The Netherlands, 1999"}],"container-title":["Lecture Notes in Computer Science","Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/3-540-45716-X_4","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,2,17]],"date-time":"2019-02-17T22:34:39Z","timestamp":1550442879000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/3-540-45716-X_4"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2002]]},"ISBN":["9783540441434","9783540457169"],"references-count":6,"URL":"https:\/\/doi.org\/10.1007\/3-540-45716-x_4","relation":{},"ISSN":["0302-9743"],"issn-type":[{"type":"print","value":"0302-9743"}],"subject":[],"published":{"date-parts":[[2002]]}}}