{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,1,20]],"date-time":"2025-01-20T05:10:51Z","timestamp":1737349851516,"version":"3.33.0"},"publisher-location":"Berlin, Heidelberg","reference-count":9,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540441434"},{"type":"electronic","value":"9783540457169"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2002]]},"DOI":"10.1007\/3-540-45716-x_45","type":"book-chapter","created":{"date-parts":[[2007,8,2]],"date-time":"2007-08-02T15:57:08Z","timestamp":1186070228000},"page":"448-457","source":"Crossref","is-referenced-by-count":1,"title":["Selective Clock-Gating for Low Power\/Low Noise Synchronous Counters"],"prefix":"10.1007","author":[{"given":"Pilar","family":"Parra","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Antonio","family":"Acosta","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Manuel","family":"Valencia","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2002,8,27]]},"reference":[{"issue":"6","key":"45_CR1","doi-asserted-by":"publisher","first-page":"630","DOI":"10.1109\/43.503933","volume":"15","author":"L. Benini","year":"1996","unstructured":"Benini, L., De Micheli, G., \u201cAutomatic Synthesis of Low Power Gated-Clock Finite-State Machines\u201d, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol.15, no. 6, June 1996., pp. 630\u2013643","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"45_CR2","doi-asserted-by":"crossref","unstructured":"Benini, L., DeMicheli, G., Macii, E., Poncino, M. y Scarsi, R. \u201cSymbolic Synthesis of Clock-Gating Logic for Power Optimization of Control-Oriented Synchronous Networks\u201d. European Design & Test Conference (EDTC-97), pp. 514\u2013520.","DOI":"10.1109\/EDTC.1997.582409"},{"key":"45_CR3","unstructured":"Piguet, C., \u201cLow-Power Design of Finite State Machines\u201d, in PATMOS, pp. 25\u201334, Bologna, Sept. 1996."},{"key":"45_CR4","doi-asserted-by":"crossref","unstructured":"A. J. Acosta, R. Jim\u00e9nez, J., M. J. Juan, Bellido, and M. Valencia, \u201cInfluence of clocking strategies on the design of low switching-noise digital and mixed-signal VLSI circuits\u201d, in 10th PATMOS, pp. 316\u2013326, G\u00f6ttingen, Sept. 2000.","DOI":"10.1007\/3-540-45373-3_33"},{"key":"45_CR5","unstructured":"Emnett, F., Biegel, M., \u201cPower Reduction through RTL Clock Gating\u201d. SNUG San Jose 2000."},{"key":"45_CR6","doi-asserted-by":"crossref","unstructured":"Stojanovic, V., OKlobdzija, V.G., \u201cComparative Analysis of Master-Slave LAtches and Flip-Flops for High-Performance and Low-Power Sistems\u201d, IEEE Journal of Solid State Circuits, Vol. 34, No. 4, April 1999.","DOI":"10.1109\/4.753687"},{"key":"45_CR7","unstructured":"Jim\u00e9nez, R., Parra, P., Sanmart\u00edn, P. and Acosta, A.J.: \u201cAnalysis of high-performance flip-flops for submicron mixed-signal applications\u201d, International Journal of Analog Integrated Circuits and Signal Processing. Kluwer Academic Publishers. (accepted)"},{"key":"45_CR8","doi-asserted-by":"crossref","unstructured":"X. Aragon\u00e8s, J. L. Gonz\u00e1lez and A. Rubio, \u201cAnalysis and Solutions for Switching Noise Coupling in Mixed-Signal ICs\u201d. Kluwer Academic Publishers, 1999.","DOI":"10.1007\/978-1-4757-3013-5"},{"key":"45_CR9","doi-asserted-by":"crossref","unstructured":"Stan, M., Tenca, A. and Ercegovac, M., \u201cLong and Fast Up\/Down Counters\u201d. IEEE Transactions on Computers, Vol. 47, No. 7, July 1998.","DOI":"10.1109\/12.709372"}],"container-title":["Lecture Notes in Computer Science","Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/3-540-45716-X_45","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,1,20]],"date-time":"2025-01-20T02:52:51Z","timestamp":1737341571000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/3-540-45716-X_45"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2002]]},"ISBN":["9783540441434","9783540457169"],"references-count":9,"URL":"https:\/\/doi.org\/10.1007\/3-540-45716-x_45","relation":{},"ISSN":["0302-9743"],"issn-type":[{"type":"print","value":"0302-9743"}],"subject":[],"published":{"date-parts":[[2002]]}}}