{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,10,6]],"date-time":"2026-10-06T19:21:11Z","timestamp":1791314471716,"version":"4.3.1"},"publisher-location":"Berlin, Heidelberg","reference-count":22,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"value":"9783540443070","type":"print"},{"value":"9783540458289","type":"electronic"}],"license":[{"start":{"date-parts":[[2002,1,1]],"date-time":"2002-01-01T00:00:00Z","timestamp":1009843200000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2002]]},"DOI":"10.1007\/3-540-45828-x_25","type":"book-chapter","created":{"date-parts":[[2007,9,21]],"date-time":"2007-09-21T13:59:11Z","timestamp":1190383151000},"page":"334-348","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":21,"title":["Processor Pipelines and Their Properties for Static WCET Analysis"],"prefix":"10.1007","author":[{"given":"Jakob","family":"Engblom","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Bengt","family":"Jonsson","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"297","published-online":{"date-parts":[[2002,10,24]]},"reference":[{"key":"25_CR1","unstructured":"ARM Ltd. ARM 9TDMI Technical Reference Manual, 3rd edition, March 2000. Document no. DDI0180A."},{"key":"25_CR2","unstructured":"P. Atanassov, R. Kirner, and P. Puschner. Using Real Hardware to Create an Accurate Timing Model for Execution-Time Analysis. In Proc. IEEE Real-Time Embedded Systems Workshop, held in conjunction with RTSS 2001, December 2001."},{"key":"25_CR3","doi-asserted-by":"crossref","unstructured":"I. Bate, G. Bernat, G. Murphy, and P. Puschner. Low-level Analysis of a Portable Java Byte Code WCET Analysis Framework. In Proc. 7 th International Conference on Real-Time Computing Systems and Applications (RTCSA\u201900), pages 39\u201348. IEEE Computer Society Press, December 2000.","DOI":"10.1109\/RTCSA.2000.896369"},{"key":"25_CR4","unstructured":"A. Colin and I. Puaut. A Modular and Retargetable Framework for Tree-Based WCET Analysis. In Proc. 13 th219 Euromicro Conference on Real-Time Systems, (ECRTS\u2019 01). IEEE Computer Society Press, June 2001."},{"key":"25_CR5","doi-asserted-by":"publisher","first-page":"61","DOI":"10.1016\/0004-3702(91)90006-6","volume":"49","author":"R. Dechter","year":"1991","unstructured":"Rina Dechter, Itay Meiri, and Judea Pearl. Temporal constraint networks. Artifical Intelligence, 49:61\u201395, 1991.","journal-title":"Artifical Intelligence"},{"key":"25_CR6","unstructured":"J. Engblom. Processor Pipelines and Static Worst-Case Execution Time Analysis. PhD thesis, Dept. of Information Technology, Uppsala University, April 2002. Acta Universitatis Upsaliensis, Dissertations from the Faculty of Science and Technology 36, http:\/\/publications.uu.se\/theses\/91-554-5228-0\/ ."},{"key":"25_CR7","unstructured":"J. Engblom and A. Ermedahl. Pipeline Timing Analysis Using a Trace-Driven Simulator. In Proc. 6 th International Conference on Real-Time Computing Systems and Applications (RTCSA\u201999). IEEE Computer Society Press, December 1999."},{"key":"25_CR8","series-title":"Lect Notes Comput Sci","volume-title":"Proc. First International Workshop on Embedded Software (EMSOFT 2001)","author":"C. Ferdinand","year":"2001","unstructured":"C. Ferdinand, R. Heckmann, M. Langenbach, F. Martin, M. Schmidt, H. Theiling, S. Thesing, and R. Wilhelm. Reliable and Precise WCET Determination for a Real-Life Processor. In Proc. First International Workshop on Embedded Software (EMSOFT 2001), LNCS 2211. Springer-Verlag, October 2001."},{"key":"25_CR9","doi-asserted-by":"crossref","unstructured":"C. Healy, R. Arnold, F. Mueller, D. Whalley, and M. Harmon. Bounding pipeline and instruction cache performance. IEEE Transactions on Computers, 48(1), January 1999.","DOI":"10.1109\/12.743411"},{"key":"25_CR10","unstructured":"J. Heinrich. MIPS R4000 Microprocessor User\u2019s Manual. MIPS Technologies Inc., 2 nd edition, 1994."},{"key":"25_CR11","unstructured":"J. L. Hennessy and D. A. Patterson. Computer Architecture A Quantitative Approach. Morgan Kaufmann Publishers Inc., 2 nd edition, 1996. ISBN 1-55860-329-8."},{"key":"25_CR12","unstructured":"Hitachi Europe Ltd. SH7700 Series Programming Manual, September 1995."},{"key":"25_CR13","unstructured":"Infineon. Instruction Set Manual for the C1 66 Family, 2nd edition, March 2001."},{"issue":"7","key":"25_CR14","doi-asserted-by":"crossref","first-page":"593","DOI":"10.1109\/32.392980","volume":"21","author":"S.-S. Lim","year":"1995","unstructured":"S.-S. Lim, Y. H. Bae, C. T. Jang, B.-D. Rhee, S. L. Min, C. Y. Park, H. Shin, K. Park, and C. S. Ki. An Accurate Worst-Case Timing Analysis for RISC Processors. IEEE Transactions on Software Engineering, 21(7):593\u2013604, July 1995.","journal-title":"IEEE Transactions on Software Engineering"},{"key":"25_CR15","unstructured":"S.-S. Lim, J. H. Han, J. Kim, and S. L. Min. A Worst Case Timing Analysis Technique for Multiple-Issue Machines. In Proc. 19 th IEEE Real-Time Systems Symposium (RTSS\u201998), December 1998."},{"key":"25_CR16","unstructured":"T. Lundqvist and P. Stenstr\u00f6m. Timing Anomalies in Dynamically Scheduled Microprocessors. In Proc. 20 th IEEE Real-Time Systems Symposium (RTSS\u201999), December 1999."},{"key":"25_CR17","unstructured":"NEC Corporation. V850 Family 32\/16-bit Single Chip Microcontroller User\u2019s Manual: Architecture, 4th edition, 1995. Document no. U10243EJ4V0UM00."},{"key":"25_CR18","unstructured":"NEC Corporation. V850E\/MS1 32\/16-bit Single Chip Microcontroller: Architecture, 3rd edition, January 1999. Document no. U12197EJ3V0UM00."},{"key":"25_CR19","unstructured":"G. Ottosson and M. Sj\u00f6din. Worst-Case Execution Time Analysis for Modern Hardware Architectures. In Proc. ACM SIGPLAN Workshop on Languages, Compilers and Tools for Real-Time Systems (LCT-RTS\u201997), June 1997."},{"key":"25_CR20","doi-asserted-by":"crossref","unstructured":"J\u00f6rn Schneider and Christian Ferdinand. Pipeline Behaviour Prediction for Superscalar Processors by Abstract Interpretation. In Proc. ACM SIGPLAN Workshop on Languages, Compilers and Tools for Embedded Systems (LCTES\u201999), May 1999.","DOI":"10.1145\/314403.314432"},{"key":"25_CR21","unstructured":"Friedhelm Stappert. Predicting pipelining and caching behaviour of hard real-time programs. In Proc. of the 9 th Euromicro Workshop on Real-Time Systems IEEE Computer Society Press, June 1997."},{"key":"25_CR22","doi-asserted-by":"crossref","unstructured":"D. Ziegenbein, F. Wolf, K. Richter, M. Jersak, and R. Ernst. Interval-Based Analysis of Software Processes. In Proc. ACM SIGPLAN Workshop on Languages, Compilers and Tools for Embedded Systems (LCTES\u20192001), June 2001.","DOI":"10.1145\/384198.384211"}],"container-title":["Lecture Notes in Computer Science","Embedded Software"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/3-540-45828-X_25","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,1,21]],"date-time":"2025-01-21T04:15:33Z","timestamp":1737432933000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/3-540-45828-X_25"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2002]]},"ISBN":["9783540443070","9783540458289"],"references-count":22,"URL":"https:\/\/doi.org\/10.1007\/3-540-45828-x_25","relation":{},"ISSN":["0302-9743"],"issn-type":[{"value":"0302-9743","type":"print"}],"subject":[],"published":{"date-parts":[[2002]]},"assertion":[{"value":"24 October 2002","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}}]}}