{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,5]],"date-time":"2025-10-05T04:18:36Z","timestamp":1759637916496,"version":"3.33.0"},"publisher-location":"Berlin, Heidelberg","reference-count":28,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540443117"},{"type":"electronic","value":"9783540458333"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2002]]},"DOI":"10.1007\/3-540-45833-6_3","type":"book-chapter","created":{"date-parts":[[2007,8,11]],"date-time":"2007-08-11T10:25:53Z","timestamp":1186827953000},"page":"27-37","source":"Crossref","is-referenced-by-count":17,"title":["Very Large Scale Spatial Computing"],"prefix":"10.1007","author":[{"given":"Andr\u00e9","family":"DeHon","sequence":"first","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2002,10,10]]},"reference":[{"unstructured":"International Technology Roadmap for Semiconductors. < http:\/\/public.itrs.net\/Files\/2001ITRS\/ >, 2001.","key":"3_CR1"},{"key":"3_CR2","series-title":"Lect Notes Comput Sci","volume-title":"FPL\u20192000","author":"E. Caspi","year":"2000","unstructured":"Eylon Caspi, Michael Chu, Randy Huang, Nicholas Weaver, Joseph Yeh, John Wawrzynek, and Andr\u00e9 DeHon. Stream Computations Organized for Reconfigurable Execution (SCORE): Introduction and Tutorial. short version appears in FPL\u20192000 (LNCS 1896), 2000."},{"issue":"4","key":"3_CR3","doi-asserted-by":"crossref","first-page":"41","DOI":"10.1109\/2.839320","volume":"33","author":"A. DeHon","year":"2000","unstructured":"Andr\u00e8 DeHon. The Density Advantage of Configurable Computing. IEEE Computer, 33(4):41\u201349, April 2000.","journal-title":"IEEE Computer"},{"doi-asserted-by":"crossref","unstructured":"Andr\u00e9 DeHon. Compact, Multilayer Layout for Butterfly Fat-Tree. In Proceedings of the Twelfth ACM Symposium on Parallel Algorithms and Architectures (SPAA\u2019 2000), pages 206\u2013215. ACM, July 2000.","key":"3_CR4","DOI":"10.1145\/341800.341824"},{"doi-asserted-by":"crossref","unstructured":"Andr\u00e9 DeHon. Rent\u2019s Rule Based Switching Requirements. In Proceedings of the System-Level Interconnect Prediction Workshop (SLIP\u20192001), pages 197\u2013204. ACM, March 2001.","key":"3_CR5","DOI":"10.1145\/368640.368870"},{"doi-asserted-by":"crossref","unstructured":"Daniel Dobberpuhl, Richard Witek, Randy Allmon, Robert Anglin, Sharon Britton, Linda Chao, Robert Conrad, Daniel Dever, Bruce Gieseke, Gregory Hoeppner, John Kowaleski, Kathryn Kuchler, Maureen Ladd, Michael Leary, Liam Madden, Edward McLellan, Derrick Meyer, James Montanaro, Donald Priore, Vidya Rajagopalan, Sridhar Samudrala, and Sribalan Santhanam. A 200MHz 64b Dual-Issue CMOS Microprocessor. In 1992 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pages 106\u2013107. IEEE, February 1992.","key":"3_CR6","DOI":"10.1109\/ISSCC.1992.200434"},{"doi-asserted-by":"crossref","unstructured":"Seth Copen Goldstein and Mihai Budiu. NanoFabrics: Spatial Computing Using Molecular Electronics. In Proceedings of the 28th Annual International Symposium on Computer Architecture, pages 178\u2013189, June 2001.","key":"3_CR7","DOI":"10.1145\/379240.379262"},{"unstructured":"L. J. Guibas, H. T. Kung, and C. D Thompson. Direct VLSI Implemenation of Combinatorial Algorithms. In Caltech Conference on VLSI, pages 509\u2013525, January 1979.","key":"3_CR8"},{"issue":"3","key":"3_CR9","doi-asserted-by":"publisher","first-page":"168","DOI":"10.1147\/sj.103.0168","volume":"10","author":"D. J. Hatfield","year":"1971","unstructured":"D. J. Hatfield and J. Gerald. Program Restructuring for Virtual Memory. IBM Systems Journal, 10(3):168\u2013192, 1971.","journal-title":"IBM Systems Journal"},{"doi-asserted-by":"crossref","unstructured":"Dzung T. Hoang. Searching Genetic Databases on Splash 2. In Duncan A. Buell and Kenneth L. Pocek, editors, Proceedings of the IEEE Workshop on FPGAs for Custom Computing Machines, pages 185\u2013191, Los Alamitos, California, April 1993. IEEE Computer Society, IEEE Computer Society Press.","key":"3_CR10","DOI":"10.1109\/FPGA.1993.279464"},{"issue":"1","key":"3_CR11","doi-asserted-by":"publisher","first-page":"96","DOI":"10.1109\/43.363121","volume":"14","author":"L. J. Hwang","year":"1995","unstructured":"L. James Hwang and Abbas El Gamal. Min-Cut Replication in Partitioned Networks. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 14(1):96\u2013106, January 1995.","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"issue":"3","key":"3_CR12","doi-asserted-by":"crossref","first-page":"223","DOI":"10.1109\/JPROC.2001.915371","volume":"89","author":"Guest Editor James Meindl. Special Issue on Limits of Semiconductor Technology","year":"2001","unstructured":"Guest Editor James Meindl. Special Issue on Limits of Semiconductor Technology. Proceedings of the IEEE, 89(3):223\u2013393, March 2001.","journal-title":"Proceedings of the IEEE"},{"unstructured":"Gilles Kahn. The Semantics of a Simple Language for Parallel Programming. In Proceedings of the IFIP CONGRESS 74, pages 471\u2013475. North-Holland Publishing Company, 1974.","key":"3_CR13"},{"issue":"1","key":"3_CR14","doi-asserted-by":"crossref","first-page":"37","DOI":"10.1109\/MC.1982.1653825","volume":"15","author":"H. T. Kung","year":"1982","unstructured":"H. T. Kung. Why Systolic Architectures? IEEE Computer, 15(1):37\u201346, January 1982.","journal-title":"IEEE Computer"},{"unstructured":"H. T. Kung and Charles E. Leiserson. Systolic Arrays (for VLSI). In Proceedings of 1978 Sparse Matrix Conference, pages 256\u2013282. Society for Industrial and Applied Mathematics, 1979.","key":"3_CR15"},{"key":"3_CR16","doi-asserted-by":"publisher","first-page":"1469","DOI":"10.1109\/T-C.1971.223159","volume":"20","author":"B. S. Landman","year":"1971","unstructured":"B. S. Landman and R. L. Russo. On Pin Versus Block Relationship for Partitions of Logic Circuits. IEEE Transactions on Computers, 20:1469\u20131479, 1971.","journal-title":"IEEE Transactions on Computers"},{"unstructured":"Charles E. Leiserson. Systolic Priority Queues. In Proceedings of the Conference on Very Large Scale Integration: Architecture, Design, and Fabrication, pages 199\u2013214. California Institute of Technology, 1979.","key":"3_CR17"},{"doi-asserted-by":"crossref","unstructured":"Michael R. Piacentino, Gooitzen S. van der Wal, and Michael W. Hansen. Reconfigurable Elements for a Video Pipeline Processor. In Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM\u201999), pages 82\u201391. IEEE, 1999.","key":"3_CR18","DOI":"10.1109\/FPGA.1999.803670"},{"doi-asserted-by":"crossref","unstructured":"Christian Plessl and Marco Platzner. Custom Computing Machines for the Set Covering Problem. In Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM\u20192002). IEEE, 2002.","key":"3_CR19","DOI":"10.1109\/FPGA.2002.1106671"},{"issue":"2","key":"3_CR20","doi-asserted-by":"publisher","first-page":"147","DOI":"10.1109\/TC.1972.5008919","volume":"21","author":"R. L. Russo","year":"1972","unstructured":"Roy L. Russo. On the Tradeoff Between Logic Performance and Circuit-to-Pin Ratio for LSI. IEEE Transactions on Computers, 21(2):147\u2013153, February 1972.","journal-title":"IEEE Transactions on Computers"},{"unstructured":"Minshine Shih and Chung-Kuan Cheng. Data Flow Partitioning for Clock Period and Latency Minimization. In Proceedings of the 31st Design Automation Conference (DAC\u201931), June 1994.","key":"3_CR21"},{"unstructured":"Reetinder Sidhu and Viktor K. Prasanna. Fast Regular Expression Matching using FPGAs. In Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM\u20192001). IEEE, 2001.","key":"3_CR22"},{"doi-asserted-by":"crossref","unstructured":"Kazumasa Suzuki, Masakazu Yamashina, Takashi Nakayama, Masanori Izumikawa, Masahiro Nomura, Hiroyuki Igura, Hideki Heiuchi, Junichi Goto, Toshiaki Inoue, Youichi Koseki, Hitoshi Abiko, Kazuhiro Okabe, Atsuki Ono, Youichi Yano, and Hachiro Yamada. A 500MHz 32b 0.4\u03bcm CMOS RISC Processor LSI. In 1994 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pages 214\u2013215. IEEE, February 1994.","key":"3_CR23","DOI":"10.1109\/ISSCC.1994.344664"},{"issue":"11","key":"3_CR24","doi-asserted-by":"crossref","first-page":"25","DOI":"10.1109\/2.803637","volume":"32","author":"D. Sylvester","year":"1999","unstructured":"Dennis Sylvester and Kurt Keutzer. Rethinking Deep-Submicron Circuit Design. IEEE Computer, 32(11):25\u201333, November 1999.","journal-title":"IEEE Computer"},{"issue":"4","key":"3_CR25","doi-asserted-by":"publisher","first-page":"410","DOI":"10.1145\/268424.268469","volume":"2","author":"H. Tomiyama","year":"1997","unstructured":"Hiroyuki Tomiyama and Hiroto Yasuura. Code Placement Techniques for Cache Miss Rate Reduction. ACM Transactions on Design Automation of Electronic Systems, 2(4):410\u2013429, October 1997.","journal-title":"ACM Transactions on Design Automation of Electronic Systems"},{"unstructured":"William Tsu, Kip Macy, Atul Joshi, Randy Huang, Norman Walker, Tony Tung, Omid Rowhani, Varghese George, John Wawrzynek, and Andr\u00e9 DeHon. HSRA: High-Speed, Hierarchical Synchronous Reconfigurable Array. In Proceedings of the International Symposium on Field Programmable Gate Arrays, pages 125\u2013134, February 1999.","key":"3_CR26"},{"doi-asserted-by":"crossref","unstructured":"John Villasenor, Brian Schoner, Kang-Ngee Chia, and Charles Zapata. Configurable Computer Solutions for Automatic Target Recognition. In Proceedings of the IEEE Workshop on FPGAs for Custom Computing Machines, pages 70\u201379. IEEE, April 1996.","key":"3_CR27","DOI":"10.1109\/FPGA.1996.564749"},{"doi-asserted-by":"crossref","unstructured":"Peixin Zhong, Margaret Martonosi, Pranav Ashar, and Sharad Malik. Accelerating Boolean Satisfiability with Configurable Hardware. In Proceedings of the 1998 IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM\u201998), pages 186\u2013195, April 1998.","key":"3_CR28","DOI":"10.1109\/FPGA.1998.707896"}],"container-title":["Lecture Notes in Computer Science","Unconventional Models of Computation"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/3-540-45833-6_3","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,1,20]],"date-time":"2025-01-20T08:05:08Z","timestamp":1737360308000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/3-540-45833-6_3"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2002]]},"ISBN":["9783540443117","9783540458333"],"references-count":28,"URL":"https:\/\/doi.org\/10.1007\/3-540-45833-6_3","relation":{},"ISSN":["0302-9743"],"issn-type":[{"type":"print","value":"0302-9743"}],"subject":[],"published":{"date-parts":[[2002]]}}}