{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T21:16:16Z","timestamp":1725484576013},"publisher-location":"Berlin, Heidelberg","reference-count":25,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540433224"},{"type":"electronic","value":"9783540458746"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2002]]},"DOI":"10.1007\/3-540-45874-3_13","type":"book-chapter","created":{"date-parts":[[2007,5,29]],"date-time":"2007-05-29T22:16:22Z","timestamp":1180476982000},"page":"224-241","source":"Crossref","is-referenced-by-count":0,"title":["A Reconfigurable Functional Unit for TriMedia\/CPU64. A Case Study"],"prefix":"10.1007","author":[{"given":"Mihai","family":"Sima","sequence":"first","affiliation":[]},{"given":"Sorin","family":"Cotofana","sequence":"additional","affiliation":[]},{"given":"Stamatis","family":"Vassiliadis","sequence":"additional","affiliation":[]},{"given":"Jos T. J.","family":"van Eijndhoven","sequence":"additional","affiliation":[]},{"given":"Kees","family":"Vissers","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2002,4,23]]},"reference":[{"unstructured":"Razdan, R., Smith, M.D.: A High Performance Microarchitecture with Hardware-Programmable Functional Units. In: 27th Annual Intl. Symposium on Microarchitecture\u2014MICRO-27, San Jose, California, (1994) 172\u2013180.","key":"13_CR1"},{"unstructured":"Wittig, R.D., Chow, P.: OneChip: An FPGA ProcessorWith Reconfigurable Logic. In: IEEE Symposium on FPGAs for Custom Computing Machines, Napa Valley, California, (1996) 126\u2013135.","key":"13_CR2"},{"doi-asserted-by":"crossref","unstructured":"Hauser, J.R., Wawrzynek, J.: Garp: A MIPS Processor with a Reconfigurable Coprocessor. In: IEEE Symposium on FPGAs for Custom Computing Machines, Napa Valley, California, (1997) 12\u201321.","key":"13_CR3","DOI":"10.1109\/FPGA.1997.624600"},{"doi-asserted-by":"crossref","unstructured":"Kastrup, B., Bink, A., Hoogerbrugge, J.: ConCISe: A Compiler-Driven CPLD-Based Instruction Set Accelerator. In: IEEE Symposium on FPGAs for Custom Computing Machines, Napa Valley, California, (1999) 92\u2013100.","key":"13_CR4","DOI":"10.1109\/FPGA.1999.803671"},{"key":"13_CR5","doi-asserted-by":"crossref","DOI":"10.1007\/b115884","volume-title":"MPEGVideo Compression Standard","author":"J.L. Mitchell","year":"1996","unstructured":"Mitchell, J.L., Pennebaker, W.B., Fogg, C.E., LeGall, D.J.: MPEGVideo Compression Standard. Chapman & Hall, NewYork, NewYork (1996)."},{"key":"13_CR6","doi-asserted-by":"crossref","first-page":"345","DOI":"10.1016\/B978-0-444-88790-0.50017-4","volume-title":"VLSI Implementations for Image Communications","author":"M.T. Sun","year":"1993","unstructured":"Sun, M.T.: Design of High-Throughput Entropy Codec. In: VLSI Implementations for Image Communications. Volume 2. Elsevier Science Publishers B.V., Amsterdam, The Netherlands (1993) 345\u2013364."},{"key":"13_CR7","volume-title":"Algorithms, Advantages, Applications","author":"K.R. Rao","year":"1990","unstructured":"Rao, K.R., Yip, P.: Discrete Cosine Transform. Algorithms, Advantages, Applications. Academic Press, San Diego, California (1990)."},{"unstructured":"Loeffler, C., Ligtenberg, A., Moschytz, G.S.: Practical Fast 1-D DCT Algorithms with 11 Multiplications. In: Intl. Conference on Acoustics, Speech, and Signal Processing (ICASSP\u2019 89), (1989) 988\u2013991.","key":"13_CR8"},{"unstructured":"van Eijndhoven, J., Sijstermans, F.: Data Processing Device and method of Computing the Cosine Transform of a Matrix. PCT Patent No.WO 9948025 (1999).","key":"13_CR9"},{"unstructured":"Sima, M., Cotofana, S., van Eijndhoven, J.T., Vassiliadis, S., Vissers, K.: 8\u00d78 IDCT Implementation on an FPGA-augmented TriMedia. In: IEEE Symposium on FPGAs for Custom Computing Machines, Rohnert Park, California, (2001).","key":"13_CR10"},{"key":"13_CR11","doi-asserted-by":"publisher","first-page":"306","DOI":"10.1109\/31.101323","volume":"38","author":"A. Mukherjee","year":"1991","unstructured":"Mukherjee, A., Ranganathan, N., Bassiouni, M.: Efficient VLSI Design for Data Transformation of Tree-Based Codes. IEEE Transactions on Circuits and Systems 38 (1991) 306\u2013314.","journal-title":"IEEE Transactions on Circuits and Systems"},{"unstructured":"Kinouchi, S., Sawada, A.: Variable Length Code Decoder. U.S. Patent No. 6,069,575 (2000).","key":"13_CR12"},{"key":"13_CR13","doi-asserted-by":"publisher","first-page":"147","DOI":"10.1109\/76.109154","volume":"1","author":"S.M. Lei","year":"1991","unstructured":"Lei, S.M., Sun, M.T.: An Entropy Coding System for Digital HDTV Applications. IEEE Transactions on Circuits and Systems for Video Technology 1 (1991) 147\u2013155.","journal-title":"IEEE Transactions on Circuits and Systems for Video Technology"},{"key":"13_CR14","doi-asserted-by":"publisher","first-page":"42","DOI":"10.1109\/54.500200","volume":"13","author":"S. Brown","year":"1996","unstructured":"Brown, S., Rose, J.: Architecture of FPGAs and CPLDs: A Tutorial. IEEE Transactions on Design and Test of Computers 13 (1996) 42\u201357.","journal-title":"IEEE Transactions on Design and Test of Computers"},{"unstructured":"DeHon, A. T. Knight, J., Tau, E., Bolotski, M., Eslick, I., Chen, D., Brown, J.: Dynamically Programmable Gate Array with Multiple Context. U.S. Patent No. 5,742,180 (1998).","key":"13_CR15"},{"doi-asserted-by":"crossref","unstructured":"Trimberger, S., Carberry, D., Johnson, A., Wong, J.: A Time-Multiplexed FPGA. In: IEEE Symposium on FPGAs for Custom Computing Machines, Napa Valley, California, (1997) 22\u201328.","key":"13_CR16","DOI":"10.1109\/FPGA.1997.624601"},{"unstructured":"***: ACEX 1K Programmable Logic Family. Altera Datasheet, San Jose, California (2000).","key":"13_CR17"},{"doi-asserted-by":"crossref","unstructured":"van Eijndhoven, J.T.J., Sijstermans, F.W., Vissers, K.A., Pol, E.J.D., Tromp, M.J.A., Struik, P., Bloks, R.H.J., van der Wolf, P., Pimentel, A.D., Vranken, H.P.E.: TriMedia CPU64 Architecture. In: Intl. Conference on Computer Design, Austin, Texas, (1999) 586\u2013592.","key":"13_CR18","DOI":"10.1109\/ICCD.1999.808601"},{"unstructured":"Sima, M., Vassiliadis, S., Cotofana, S., van Eijndhoven, J.T., Vissers, K.: A Taxonomy of Custom Computing Machines. In: First PROGRESS Workshop on Embedded Systems, Utrecht, The Netherlands, (2000) 87\u201393.","key":"13_CR19"},{"doi-asserted-by":"crossref","unstructured":"Pol, E.J.D., Aarts, B.J.M., van Eijndhoven, J.T.J., Struik, P., Sijstermans, F.W., Tromp, M.J.A., van de Waerdt, J.W., van der Wolf, P.: TriMedia CPU64 Application Development Environment. In: Intl. Conference on Computer Design, Austin, Texas, (1999) 593\u2013598.","key":"13_CR20","DOI":"10.1109\/ICCD.1999.808602"},{"unstructured":"van Eijndhoven, J.: 16-bit compliant software IDCT on TriMedia\/CPU64. Internal Report, Philips Research Laboratories (1997).","key":"13_CR21"},{"unstructured":"***: IEEE Standard Specifications for the Implementations of 8\u00d78 Inverse Discrete Cosine Transform. IEEE Std 1180-1990 (1991).","key":"13_CR22"},{"key":"13_CR23","doi-asserted-by":"publisher","first-page":"97","DOI":"10.1109\/30.370315","volume":"41","author":"S.B. Choi","year":"1995","unstructured":"Choi, S.B., Lee, M.H.: High Speed Pattern Matching for a Fast Huffman Decoder. IEEE Transactions on Consumer Electronics 41 (1995) 97\u2013103.","journal-title":"IEEE Transactions on Consumer Electronics"},{"unstructured":"Min, K.-Y., Chong, J.-W.: A Memory-Efficient VLC decoder Architecture for MPEG-2 Application. In: IEEEWorkshop on Signal Processing Systems, Lafayette, Louisiana, (2000) 43\u201349.","key":"13_CR24"},{"unstructured":"Pol, E.J.D.: VLD Performance on TriMedia\/CPU64. Internal Report, Philips Research Laboratories (2000).","key":"13_CR25"}],"container-title":["Lecture Notes in Computer Science","Embedded Processor Design Challenges"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/3-540-45874-3_13","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,2,16]],"date-time":"2019-02-16T19:39:55Z","timestamp":1550345995000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/3-540-45874-3_13"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2002]]},"ISBN":["9783540433224","9783540458746"],"references-count":25,"URL":"https:\/\/doi.org\/10.1007\/3-540-45874-3_13","relation":{},"ISSN":["0302-9743"],"issn-type":[{"type":"print","value":"0302-9743"}],"subject":[],"published":{"date-parts":[[2002]]}}}