{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,1,17]],"date-time":"2025-01-17T05:21:51Z","timestamp":1737091311263,"version":"3.33.0"},"publisher-location":"Berlin, Heidelberg","reference-count":63,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540433224"},{"type":"electronic","value":"9783540458746"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2002]]},"DOI":"10.1007\/3-540-45874-3_18","type":"book-chapter","created":{"date-parts":[[2007,5,30]],"date-time":"2007-05-30T02:16:22Z","timestamp":1180491382000},"page":"307-325","source":"Crossref","is-referenced-by-count":3,"title":["A Java-Enabled DSP"],"prefix":"10.1007","author":[{"given":"C. John","family":"Glossner","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Michael","family":"Schulte","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Stamatis","family":"Vassiliadis","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2002,4,23]]},"reference":[{"key":"18_CR1","doi-asserted-by":"crossref","unstructured":"J. Eyre and J. Bier. DSP Processors Hit the Mainstream. IEEE Computer, pages 51\u201359, August 1998.","DOI":"10.1109\/2.707617"},{"key":"18_CR2","unstructured":"Junko Yoshida. Java chip vendors set for cellular skirmish. EE Times, January 30 2001."},{"key":"18_CR3","doi-asserted-by":"crossref","DOI":"10.1109\/9780470544433","volume-title":"DSP Processor Fundamentals","author":"P. Lapley","year":"1997","unstructured":"P. Lapley. DSP Processor Fundamentals. IEEE press, New York, 1997."},{"key":"18_CR4","unstructured":"M. Saghir, P. Chow, and C. G. Lee. Towards Better DSP Architecture and Compilers. In Proceedings of the International Conference on Signal Processing Applications and Technology, pages 658\u2013664, October 1994."},{"key":"18_CR5","unstructured":"Texas Instruments. TMS320C54x DSP Reference Set. Volume 1: CPU and Perhipherals. Technical Report SPRU131E, Texas Instruments, June 1998."},{"key":"18_CR6","unstructured":"Je. Bier. DSP16xxx Targets Communictaions Apps. Microprocessor Report, 11(12), 1997."},{"key":"18_CR7","doi-asserted-by":"crossref","unstructured":"G. Ungerboeck, D. Maiwald, H. P. Kaeser, P. R. Chevillat, and J. P. Beraud. Architecture of a Digital Signal Processor. IBM Journal of Research and Development, 29(2), 1985.","DOI":"10.1147\/rd.292.0132"},{"key":"18_CR8","unstructured":"N. L. Bernbaum, B. Blaner, D. E. Carmon, J. K. D\u2019Addio, F. E. Grieco, A. M. Jacoutot, M. A. Locker, B. Marshall, D. W. Milton, C. R. Ogilvie, P. M. Schanely, P. C. Stabler, and M. Turcotte. The IBM Mwave 3780i DSP. In Proceedings of the 1996 International Conference on Signal Processing Applications and Technology (ICSPAT\u2019 96), pages 1287\u20131291, Boston, MA, October 1996."},{"key":"18_CR9","unstructured":"Tom R. Halfhill. TI Cores Accelerate DSP Arms Race. Microprocessor Report, March 6 2000."},{"key":"18_CR10","unstructured":"J. Eyre and J. Bier. Carmel Enables Customizable DSP. Microprocessor Report, 12(17), December 1998."},{"key":"18_CR11","unstructured":"LSI Corporation. LSI402Z Digital Signal Processor. LSI Corporation, r20012 edition, 1999."},{"key":"18_CR12","unstructured":"Gerald G. Pechanek, C. John Glossner, William F. Lawless, Daniel H. McCabe, Chris H. L. Moller, and Steven J. Walsh. A Machine Organization and Architecture for Highly Parallel, Scalable, Single Chip DSPs. In Proceedings of the 1995 DSPx Technical Program Conference and Exhibition, pages 42\u201350, San Jose, California, May 1995."},{"key":"18_CR13","unstructured":"Gerald G. Pechanek, Mihilo Stojancic, Stamatis Vassiliadis, and C. John Glossner. M.F.A.S.T.: A Single Chip, Highly Parallel Image Processing Architecture. In Proceedings IEEE International Conference on Image Processing, volume I, pages 1375\u20131379, Arlington, Virginia, October 1995. IEEE Press."},{"key":"18_CR14","unstructured":"Gerald G. Pechanek, Charles W. Kurak, C. John Glossner, Chris H. L. Moller, and Steven J. Walsh. M.F.A.S.T.: A Highly Parallel Single Chip DSP with a 2D IDCT Example. In Proceeding of the International Conference on Signal Processing Applications and Technology, pages 69\u201372, Boston, Mass., October 1995."},{"key":"18_CR15","unstructured":"Gerald G. Pechanek, C. John Glossner, Zhiyong Li, Chris H. L. Moller, and Stamatis Vassiliadis. Tensor Product FFT\u2019s on M.F.A.S.T.: A Highly Parallel Single Chip DSP. In Proceedings of DSP 95\u2014Digital Signal Processing and Its Applications, Paris, France, October 1995."},{"key":"18_CR16","unstructured":"B. Case. Philips hopes to displace DSPs with VLIW. Microprocessor Report, pages 12\u201315, December 1997."},{"key":"18_CR17","unstructured":"C. P. Feigel. TI Introduces Four-Processor DSP Chip. Microprocessor Report, 8(4), March 28 1994."},{"key":"18_CR18","unstructured":"Dave Epstein. Chromatic Raises the Multimedia Bar. Microprocessor Report, 9(14), October 28 1995."},{"key":"18_CR19","doi-asserted-by":"crossref","unstructured":"A. Peleg and U. Weiser. MMX technology extension to the Intel architecture. IEEE Micro, pages 42\u201350, August 1996.","DOI":"10.1109\/40.526924"},{"key":"18_CR20","doi-asserted-by":"crossref","unstructured":"H. Nguyen and L. K. John. Exploiting SIMD Parallelism in DSP and Multimedia Algorithms Using the AltiVec Technology. In Proceedings of the International Conference on Supercomputing, pages 11\u201320, 1999.","DOI":"10.1145\/305138.305150"},{"key":"18_CR21","unstructured":"J. C. Bier, A. Shoham, H. Hakkarainen, O. Wolf, G. Blalock, and Philip D. Lapsley. DSP on General-Purpose Processors: Performance, Architecture, Pitfalls. Berkeley Design Technology, Inc., 1997."},{"key":"18_CR22","unstructured":"O. Wolf and J. Bier. StarCore Launches First Architecture. Microprocessor Report, 12(14), October 1998."},{"key":"18_CR23","unstructured":"O. Wolf and J. Bier. TigerSHARC Sinks Teeth Into VLIW. Microprocessor Report, 12(16), December 1998."},{"issue":"1","key":"18_CR24","doi-asserted-by":"publisher","first-page":"66","DOI":"10.1109\/40.820055","volume":"20","author":"J. Fridman","year":"2000","unstructured":"J. Fridman and Z. Greenfield. The TigerSHARC DSP Architecture. IEEE Micro, 20(1):66\u201376, January 2000.","journal-title":"IEEE Micro"},{"key":"18_CR25","unstructured":"J. Turley and H. Hakkarainen. TI\u2019s New C6x Screams at 1,600 MIPS. Microprocessor Report, 11(2), 1997."},{"key":"18_CR26","series-title":"Lect Notes Comput Sci","doi-asserted-by":"crossref","first-page":"761","DOI":"10.1007\/3-540-48311-X_107","volume-title":"ManArray processor interconnection network: an introduction","author":"G. G. Pechanek","year":"1999","unstructured":"Gerald G. Pechanek, Stamatis Vassiliadis, and Nikos Pitsianis. ManArray processor interconnection network: an introduction. In Euro-Par\u2019 99 Parallel Processing Proceedings. (Lecture notes in computer science), pages 761\u2013765, Toulouse, France, August\/September 1999. Springer, Berlin."},{"key":"18_CR27","doi-asserted-by":"crossref","unstructured":"Gerald G. Pechanek and Stamatis Vassiliadis. The ManArray Embedded Processor Architecture. In Proceedings of the 26-th Euromicro Conference: Informatics: inventing the future, volume I, pages 348\u2013355, Maastrict, The Netherlands, September 5\u20137 2000.","DOI":"10.1109\/EURMIC.2000.874652"},{"key":"18_CR28","doi-asserted-by":"crossref","unstructured":"Bryan Ackland and Paul D\u2019Arcy. A New Generation of DSP Architectures. In Proceedings of the 1999 Custom Integrated Circuits Conference, pages 531\u2013536, 1999.","DOI":"10.1109\/CICC.1999.777337"},{"volume-title":"The Java Language Specification","year":"1996","key":"18_CR29","unstructured":"James Gosling, Bill Joy, and Guy Steele, editors. The Java Language Specification. The Java Series. Addison-Wesley, Reading, MA, USA, 1996."},{"key":"18_CR30","series-title":"Technical report","volume-title":"The Java Language Environment: A White Paper","author":"J. Gosling","year":"1995","unstructured":"James Gosling and Henry McGilton. The Java Language Environment: A White Paper. Technical report, Sun Microsystems, Mountain View, California, October 1995. Available from ftp.javasoft.com\/docs ."},{"key":"18_CR31","volume-title":"The Java Virtual Machine Specification","author":"T. Lindholm","year":"1997","unstructured":"Tim Lindholm and Frank Yellin. The Java Virtual Machine Specification. The Java Series. Addison-Wesley, Reading, MA, USA, 1997."},{"key":"18_CR32","doi-asserted-by":"crossref","unstructured":"Cheng-Hsueh A. Hsieh, John C. Gyllenhaal, and Wen mei W. Hwu. Java Bytecode to Native Code Translation: The Caffeine Prototype and Preliminary Results. In Proceeding of the 29th Annual Internation Symposium on Microarchitecture (MICRO-29), pages 90\u201397, Los Alamitos, CA, USA, December 2\u20134 1996. IEEE Computer Society Press.","DOI":"10.1109\/MICRO.1996.566453"},{"key":"18_CR33","doi-asserted-by":"crossref","unstructured":"Ali-Reza Adl-Tabatabai, Michal Cierniak, Guie-Yuan Lueh, Vishesh M. Parikh, and James M. Stichnoth. Fast, effective code generation in a just-in-time Java compiler. In Proceeding of the ACM SIGPLAN\u2019 98 conference on Programming Language Design and Implementation (PLDI\u201998), volume 33, pages 280\u2013290. Association for Computing Machinery, May 1998.","DOI":"10.1145\/277650.277740"},{"key":"18_CR34","series-title":"Technical Report","volume-title":"JIT vs. Offline Compilers: Limits and Benefits of Bytecode Compilation","author":"G. Muller","year":"1996","unstructured":"Gilles Muller, Barbara Moura, Fabrice Bellard, and Charles Consel. JIT vs. Offline Compilers: Limits and Benefits of Bytecode Compilation. Technical Report 1063, IRISA, Campus de Beaulieu, 35042 Rennes Cedex, France, December 1996. http:\/\/www.irisa.fr ."},{"key":"18_CR35","unstructured":"Sun Microsystems. The Java Hotspot Performance Engine Architecture. Sun Microsystems, 1999. http:\/\/java.sun.com\/ products\/ hotspot\/ whitepaper.html ."},{"key":"18_CR36","unstructured":"Kemal Ebcioglu, Eric R. Altman, and Erdem Hokenek. A Java ILP Machine Based on Fast Dynamic Compilation. In IEEE MASCOTS International Workshop on Security and Efficiency Aspects of Java, Eilat, Israel, January 9\u201310 1997. IEEE Computer Society Press."},{"issue":"4","key":"18_CR37","doi-asserted-by":"publisher","first-page":"1063","DOI":"10.1002\/(SICI)1096-9128(199711)9:11<1063::AID-CPE344>3.0.CO;2-G","volume":"9","author":"M. Cierniak","year":"1997","unstructured":"Michal Cierniak and Wei Li. Just-in-time optimizations for high-performance Java programs. Concurrency: Practice and Experience, 9(4):1063\u20131073, November 1997.","journal-title":"Concurrency: Practice and Experience"},{"key":"18_CR38","unstructured":"Todd A. Proebsting, Gregg Townsend, Patrick Bridges, John H. Hartman, Tim Newsham, and Scott A. Watterson. Toba: Java For Applications\u2014A Way Ahead of Time (WAT) Compiler. In Proceedings Third Conference on Object-Oriented Technologies and Systems (COOTS\u201997), 1997."},{"key":"18_CR39","unstructured":"Hewlett Packard. HP Turbo Chai Release 2.0. Hewlett-Packard, May 1999. http:\/\/www.hp.com\/emso\/products\/turbochai\/TchaiPDF.pdf ."},{"key":"18_CR40","doi-asserted-by":"crossref","unstructured":"John Glossner, Jesse Thilo, and Stamatis Vassiliadis. Java Signal Processing: FFT\u2019s with bytecodes. In Proceedings of the 1998 ACM Workshop on Java for High-Performance Network Computing, Stanford University, Palo Alto, California, February 28 and March 1 1998.","DOI":"10.1002\/(SICI)1096-9128(199809\/11)10:11\/13<1173::AID-CPE403>3.0.CO;2-1"},{"issue":"11","key":"18_CR41","doi-asserted-by":"publisher","first-page":"1173","DOI":"10.1002\/(SICI)1096-9128(199809\/11)10:11\/13<1173::AID-CPE403>3.0.CO;2-1","volume":"10","author":"J. Glossner","year":"1998","unstructured":"John Glossner, Jesse Thilo, and Stamatis Vassiliadis. Java Signal Processing: FFT\u2019s with bytecodes. Journal of Concurrency and Experience, 10(11\u201313):1173\u20131178, 1998.","journal-title":"Journal of Concurrency and Experience"},{"key":"18_CR42","unstructured":"Cygnus. Gcj compiler, 1999."},{"key":"18_CR43","series-title":"Technical Report","volume-title":"picoJava I Microprocessor Core Architecture","author":"Sun Microelectronics","year":"1996","unstructured":"Sun Microelectronics. picoJava I Microprocessor Core Architecture. Technical Report WPR-0014-01, Sun Microsystems, Mountain View, California, November 1996. Available from http:\/\/www.sun.com\/ sparc\/ whitepapers\/ wpr-0014-01 ."},{"key":"18_CR44","unstructured":"Marc Tremblay and Micahel O\u2019Connor. picoJava: A Hardware Implementation of the Java Virtual Machine. In Hotchips Presentation, 1996."},{"issue":"10","key":"18_CR45","doi-asserted-by":"crossref","first-page":"22","DOI":"10.1109\/2.722273","volume":"31","author":"H. McGhan","year":"1998","unstructured":"Harlan McGhan and Mike O\u2019Connor. PicoJava: A Direct Execution Engine For Java Bytecode. IEEE Computer, 31(10):22\u201330, October 1998.","journal-title":"IEEE Computer"},{"issue":"5","key":"18_CR46","doi-asserted-by":"crossref","first-page":"333","DOI":"10.1049\/ip-cdt:19982200","volume":"145","author":"L. C. Chang","year":"1998","unstructured":"L. C. Chang, L. R. Ton, M. F. Kao, and C. P. Chung. Stack operations folding in Java processors. IEE Proceedings\u2014Computers and Digital Techniques, 145(5):333\u2013343, September 1998.","journal-title":"IEE Proceedings\u2014Computers and Digital Techniques"},{"key":"18_CR47","doi-asserted-by":"crossref","unstructured":"Lee-Ren Ton, Lung-Chung Chang, Min-Fu Kao, Han-Min Tseng, Shi-Sheng Shang, Ruey-Liang Ma, Dze-Chaung Wang, and Chung-Ping Chung. Instruction Folding in Java Processor. In 1997 International Conference on Parallel and Distributed Systems, pages 138\u2013143, Seoul, Korea, December 12\u201313 1997. IEEE Computer Society Press.","DOI":"10.1109\/ICPADS.1997.652541"},{"key":"18_CR48","series-title":"Technical Report","volume-title":"Sun Microelectronic\u2019s picoJava I Posts Outstanding Performance","author":"Sun Microelectronics","year":"1996","unstructured":"Sun Microelectronics. Sun Microelectronic\u2019s picoJava I Posts Outstanding Performance. Technical Report WPR-0015-01, Sun Microsystems, Mountain View, California, November 1996. Available from http:\/\/www.sun.com\/ sparc\/ whitepapers\/wpr-0015-01 ."},{"key":"18_CR49","doi-asserted-by":"crossref","unstructured":"James Gosling. Java Intermediate Bytecodes. In ACM SIGPLAN Notices, pages 111\u2013118, New York, NY, January 1995. Association for Computing Machinery. ACM SIGPLAN Workshop on Intermediate Representations (IR95).","DOI":"10.1145\/202529.202541"},{"key":"18_CR50","doi-asserted-by":"crossref","unstructured":"J. Glossner and S. Vassiliadis. Delft-Java Dynamic Translation. In Proceedings of the 25th EUROMICRO conference (EUROMICRO\u2019 99), volume 1, Milan, Italy, September 8\u201310 1999.","DOI":"10.1109\/EURMIC.1999.794446"},{"key":"18_CR51","doi-asserted-by":"crossref","unstructured":"John Glossner and Stamatis Vassiliadis. Delft-Java Link Translation Buffer. In Proceedings of the 24th EUROMICRO conference, volume 1, pages 221\u2013228, Vasteras, Sweden, August 25\u201327 1998.","DOI":"10.1109\/EURMIC.1999.794446"},{"key":"18_CR52","series-title":"Lect Notes Comput Sci","doi-asserted-by":"crossref","first-page":"766","DOI":"10.1007\/BFb0002811","volume-title":"The Delft-Java Engine: An Introduction","author":"C. J. Glossner","year":"1997","unstructured":"C. John Glossner and Stamatis Vassiliadis. The Delft-Java Engine: An Introduction. In Lecture Notes In Computer Science. Third International Euro-Par Conference (Euro-Par\u201997 Parallel Processing), pages 766\u2013770, Passau, Germany, Aug. 26\u201329 1997. Springer-Verlag."},{"key":"18_CR53","volume-title":"Threads Primer: A Guide to Multithreaded Programming","author":"B. Lewis","year":"1996","unstructured":"Bil Lewis and Daniel J. Berg. Threads Primer: A Guide to Multithreaded Programming. SunSoft Press\u2014A Prentice Hall Title, Mountain View, California, 1996."},{"issue":"11","key":"18_CR54","first-page":"79","volume":"21","author":"P. Wayner","year":"1996","unstructured":"Peter Wayner. Sun gambles on java chips. Byte, 21(11):79\u201385, November 1996.","journal-title":"Byte"},{"issue":"1","key":"18_CR55","doi-asserted-by":"crossref","first-page":"59","DOI":"10.1147\/rd.381.0059","volume":"38","author":"S. Vassiliadis","year":"1994","unstructured":"S. Vassiliadis, B. Blaner, and R. J. Eickemeyer. SCISM: A Scalable Compound Instruction Set Machine. IBM Journal of Research and Development, 38(1):59\u201378, January 1994.","journal-title":"IBM Journal of Research and Development"},{"issue":"3","key":"18_CR56","doi-asserted-by":"publisher","first-page":"257","DOI":"10.1109\/12.272427","volume":"43","author":"J. Philips","year":"1994","unstructured":"James Philips and Stamatis Vassiliadis. High-performance 3-1 interlock collapsing ALU\u2019s. IEEE Transactions on Computers, 43(3):257\u2013268, March 1994.","journal-title":"IEEE Transactions on Computers"},{"issue":"4","key":"18_CR57","first-page":"12","volume":"10","author":"B. Case","year":"1996","unstructured":"Brian Case. Implementing the java virtual machine. Microprocessor Report, 10(4):12\u201317, March 25 1996.","journal-title":"Microprocessor Report"},{"issue":"7","key":"18_CR58","doi-asserted-by":"publisher","first-page":"825","DOI":"10.1109\/12.237723","volume":"42","author":"S. Vassiliadis","year":"1993","unstructured":"Stamatis Vassiliadis, James Phillips, and Bart Blanar. Interlock Collapsing ALU\u2019s. IEEE Transactions on Computers, 42(7):825\u2013839, July 1993.","journal-title":"IEEE Transactions on Computers"},{"key":"18_CR59","doi-asserted-by":"publisher","first-page":"25","DOI":"10.1147\/rd.111.0025","volume":"II","author":"R. M. Tomasulo","year":"1967","unstructured":"R. M. Tomasulo. An Efficient Algorithm for Exploiting Multiple Arithmetic Units. IBM Journal of Research and Development, II:25\u201333, 1967.","journal-title":"IBM Journal of Research and Development"},{"issue":"7","key":"18_CR60","doi-asserted-by":"publisher","first-page":"7","DOI":"10.1145\/1216461.1216464","volume":"1","author":"W. Munsil","year":"1998","unstructured":"Wes Munsil and Chia-Jiu Wang. Reducing Stack Usage in Java Bytecode Execution. Computer Architecture News, 1(7):7\u201311, March 1998.","journal-title":"Computer Architecture News"},{"key":"18_CR61","unstructured":"Yamin Li, Sanli Li, Xianzhu Wang, and Wanming Chu. JAViR-Exploiting Instruction Level Parallelism for JAVA Machine by Using Virtual Register. In The Second European IASTED International Conference on Parallel and Distributed Systems, Vienna, Austria, July 1\u20133 1998."},{"key":"18_CR62","unstructured":"Advancel Logic Corporation. TinyJ Processor Core Product Datasheet. Datasheet, July 1999."},{"key":"18_CR63","unstructured":"Patriot Scientific Corporation. Psc1000\/a microprocessor datasheet. Patriot Scientific, 1997. http:\/\/www.ptsc.com\/downloads\/ psc1000\/specs\/datasheet.pdf ."}],"container-title":["Lecture Notes in Computer Science","Embedded Processor Design Challenges"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/3-540-45874-3_18","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,1,16]],"date-time":"2025-01-16T19:25:15Z","timestamp":1737055515000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/3-540-45874-3_18"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2002]]},"ISBN":["9783540433224","9783540458746"],"references-count":63,"URL":"https:\/\/doi.org\/10.1007\/3-540-45874-3_18","relation":{},"ISSN":["0302-9743"],"issn-type":[{"type":"print","value":"0302-9743"}],"subject":[],"published":{"date-parts":[[2002]]}}}