{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T21:42:55Z","timestamp":1725486175820},"publisher-location":"Berlin, Heidelberg","reference-count":19,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540433699"},{"type":"electronic","value":"9783540459378"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2002]]},"DOI":"10.1007\/3-540-45937-5_18","type":"book-chapter","created":{"date-parts":[[2007,6,6]],"date-time":"2007-06-06T21:39:18Z","timestamp":1181165958000},"page":"247-261","source":"Crossref","is-referenced-by-count":1,"title":["Global Variable Promotion: Using Registers to Reduce Cache Power Dissipation"],"prefix":"10.1007","author":[{"given":"Andrea G. M.","family":"Cilio","sequence":"first","affiliation":[]},{"given":"Henk","family":"Corporaal","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2002,3,28]]},"reference":[{"doi-asserted-by":"crossref","unstructured":"David Brooks, Vivek Tiwari, and Margaret Martonosi. Wattch: A framework for architectural-level power analysis and optimizations. In Proceedings of the 27th Annual International Symposium on Computer Architecture, pages 83\u201394, Vancouver, British Columbia, June 12\u201314, 2000.","key":"18_CR1","DOI":"10.1145\/339647.339657"},{"doi-asserted-by":"crossref","unstructured":"Fred C. Chow. Minimizing register usage penalty at procedure calls. In SIGPLAN\u2019 88 Conference on Programming Language Design and Implementation, pages 85\u201394, 1988.","key":"18_CR2","DOI":"10.1145\/53990.53999"},{"doi-asserted-by":"crossref","unstructured":"Andrea G. M. Cilio and Henk Corporaal. A linker for effective whole-program optimizations. In Proceedings of HPCN, Amsterdam, The Netherlands, April 1999.","key":"18_CR3","DOI":"10.1007\/BFb0100625"},{"unstructured":"Henk Corporaal. Microprocessor Architectures; from VLIW to TTA. John Wiley, 1997. ISBN 0-471-97157-X.","key":"18_CR4"},{"issue":"9","key":"18_CR5","doi-asserted-by":"publisher","first-page":"1258","DOI":"10.1109\/4.535411","volume":"31","author":"R. Gonzalez","year":"1996","unstructured":"R. Gonzalez and M. Horowitz. Energy dissipation in general purpose microprocessors. IEEE Journal of Solid-State Circuits, 31(9):1258\u201366, September 1996.","journal-title":"IEEE Journal of Solid-State Circuits"},{"unstructured":"Stanford Compiler Group. The SUIF Library. Stanford University, 1994.","key":"18_CR6"},{"unstructured":"Jan Hoogerbrugge. Instruction scheduling for trimedia. Journal of Instruction-Level Parallelism, 1(1\u20132), 1999.","key":"18_CR7"},{"unstructured":"J. Janssen. Compilation Strategies for Transport Triggered Architectures. PhD thesis, Delft University of Technology, 2001.","key":"18_CR8"},{"unstructured":"Johan Janssen and Henk Corporaal. Registers on demand: an integrated region scheduler and register allocator. In Conference on Compiler Construction, April 1998.","key":"18_CR9"},{"key":"18_CR10","volume-title":"Proceedings of the 1996 international symposium on Low power electronics and design","author":"M. B. Kamble","year":"1997","unstructured":"M. B. Kamble and K. Ghose. Analytical energy dissipation models for low-power caches. In Proceedings of the 1996 international symposium on Low power electronics and design, Monterey, CA USA, August 12\u201314, 1997. ACM."},{"doi-asserted-by":"crossref","unstructured":"M. B. Kamble and K. Ghose. Energy-efficiency of vlsi caches: a comparative study. In Proceedings Tenth International Conference on VLSI Design, pages 261\u20137. IEEE, January 1997.","key":"18_CR11","DOI":"10.1109\/ICVD.1997.568087"},{"doi-asserted-by":"crossref","unstructured":"Johnson Kin, Munish Gupta, and William H. Mangione-Smith. Filtering memory references to increase energy efficiency. IEEE Transactions on Computers, 49(1), January 2000.","key":"18_CR12","DOI":"10.1109\/12.822560"},{"unstructured":"Hsien-Hsien S. Lee and Gary S. Tyson. Region-based caching: An efficient memory architecture for embedded processors. In CASES, San Jose, CA, November 2000.","key":"18_CR13"},{"key":"18_CR14","series-title":"Technical report","volume-title":"An integrated cache timing and power model","author":"G. Reinman","year":"1999","unstructured":"G. Reinman and N. P. Jouppi. An integrated cache timing and power model. Technical report, COMPAQ Western Research Lab, Palo Alto, California, 1999."},{"doi-asserted-by":"crossref","unstructured":"Vatsa Santhanam and Daryl Odnert. Register allocation across procedure and module boundaries. In Proceedings of the Conference on Programming Language Design and Implementation, pages 28\u201339, 1990.","key":"18_CR15","DOI":"10.1145\/93542.93551"},{"unstructured":"Michael D. Smith. Extending SUIF for Machine-dependent Optimizations. In Proceedings of the First SUIF Workshop, January 1996.","key":"18_CR16"},{"doi-asserted-by":"crossref","unstructured":"Peter A. Steenkiste and John L. Hennessy. A simple interprocedural register allocation algorithm and its effectiveness for lisp. TOPLAS, 11(1), 1989.","key":"18_CR17","DOI":"10.1145\/59287.59289"},{"doi-asserted-by":"crossref","unstructured":"David W. Wall. Register windows vs. register allocation. Technical Report 7, Western Research Laboratory, Digital Equipment Corporation, December 1987.","key":"18_CR18","DOI":"10.1145\/960116.53997"},{"unstructured":"S. J. E. Wilton and N. P. Jouppi. An enhanced access and cycle time model. Technical Report 5, Digital Western Research laboratory, Palo Alto, California, July 1994.","key":"18_CR19"}],"container-title":["Lecture Notes in Computer Science","Compiler Construction"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/3-540-45937-5_18","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,4,22]],"date-time":"2020-04-22T16:33:59Z","timestamp":1587573239000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/3-540-45937-5_18"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2002]]},"ISBN":["9783540433699","9783540459378"],"references-count":19,"URL":"https:\/\/doi.org\/10.1007\/3-540-45937-5_18","relation":{},"ISSN":["0302-9743"],"issn-type":[{"type":"print","value":"0302-9743"}],"subject":[],"published":{"date-parts":[[2002]]}}}