{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T15:41:05Z","timestamp":1725550865862},"publisher-location":"Berlin, Heidelberg","reference-count":8,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540441083"},{"type":"electronic","value":"9783540461173"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2002]]},"DOI":"10.1007\/3-540-46117-5_131","type":"book-chapter","created":{"date-parts":[[2010,3,29]],"date-time":"2010-03-29T21:14:23Z","timestamp":1269897263000},"page":"1160-1163","source":"Crossref","is-referenced-by-count":2,"title":["A Reconfigurable Processor Architecture"],"prefix":"10.1007","author":[{"given":"Adronis","family":"Niyonkuru","sequence":"first","affiliation":[]},{"given":"G\u00f6ran","family":"Eggers","sequence":"additional","affiliation":[]},{"given":"Hans Christoph","family":"Zeidler","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2002,8,16]]},"reference":[{"key":"131_CR1","unstructured":"M. J. Wirthlin, B. L. Hutchings, \u201dA Dynamic Instruction Set Computer\u201d, Proc. IEEE Work. FPGAs for Custom Computing Machines, IEEE CS Press, April 1995"},{"key":"131_CR2","first-page":"605","volume-title":"Lecture Notes in Computer Science","author":"Eylon Caspi","year":"2000","unstructured":"E. Caspi et al., \u201dStream Computations Organized for Reconfigurable Execution (SCORE)\u201d, Proc. 10th Int. Conf. Field-Programmable Logic and Applications, Springer-Verlag, Aug. 2000"},{"key":"131_CR3","doi-asserted-by":"crossref","unstructured":"S.C. Goldstein et al. \u201dPipeRench: A Reconfigurable Architecture and Compiler\u201d, IEEE Computer, Vol. 33, No. 4, April 2000","DOI":"10.1109\/2.839324"},{"key":"131_CR4","unstructured":"S. Sawitzki, A. Gratz, R.G. Spallek, \u201dCoMPARE: A simple processor architecture exploiting instruction level parallelism\u201d, Proc. 5th Australasian Conf. Parallel and Real-Time Systems, Springer-Verlag, 1998"},{"key":"131_CR5","doi-asserted-by":"crossref","unstructured":"M. Dales, \u201dThe Proteus Processor-A Conventional CPU with Reconfigurable Functionality\u201d, Proc. 9th Int. Conf. Field-Programmable Logic and Applications, Springer-Verlag, Sept. 1999","DOI":"10.1007\/978-3-540-48302-1_49"},{"key":"131_CR6","unstructured":"J. L. Hennessy, D. A. Patterson, \u201dComputer Architecture: A Quantitative Approach\u201d, Morgan Kaufmann Publishers, Inc., Second Edition, 1996"},{"key":"131_CR7","unstructured":"Xilinx, Inc. \u201dVirtex-II 1.5V Field-Programmable Gate Arrays\u201d, Advance Product Specification, April 2001"},{"key":"131_CR8","unstructured":"ARM Limited, \u201dARM Architecture Reference Manual\u201d, 2000"}],"container-title":["Lecture Notes in Computer Science","Field-Programmable Logic and Applications: Reconfigurable Computing Is Going Mainstream"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/3-540-46117-5_131","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,5,27]],"date-time":"2019-05-27T19:13:46Z","timestamp":1558984426000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/3-540-46117-5_131"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2002]]},"ISBN":["9783540441083","9783540461173"],"references-count":8,"URL":"https:\/\/doi.org\/10.1007\/3-540-46117-5_131","relation":{},"ISSN":["0302-9743"],"issn-type":[{"type":"print","value":"0302-9743"}],"subject":[],"published":{"date-parts":[[2002]]}}}