{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,19]],"date-time":"2025-02-19T19:40:07Z","timestamp":1739994007586,"version":"3.37.3"},"publisher-location":"Berlin, Heidelberg","reference-count":14,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540441083"},{"type":"electronic","value":"9783540461173"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2002]]},"DOI":"10.1007\/3-540-46117-5_28","type":"book-chapter","created":{"date-parts":[[2010,3,29]],"date-time":"2010-03-29T21:14:23Z","timestamp":1269897263000},"page":"263-270","source":"Crossref","is-referenced-by-count":10,"title":["TDR: A Distributed-Memory Parallel Routing Algorithm for FPGAs"],"prefix":"10.1007","author":[{"given":"Luc\u00eddio A.F.","family":"Cabral","sequence":"first","affiliation":[]},{"given":"J\u00falio S.","family":"Aude","sequence":"additional","affiliation":[]},{"given":"Nelson","family":"Maculan","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2002,8,16]]},"reference":[{"key":"28_CR1","doi-asserted-by":"crossref","unstructured":"P. K. Chan and M. Schlag, \u201cAcceleration of an FPGA router,\u201d in Proc. 1997 IEEE Workshop FPGAs for Custom Computing Machines, 1997, pp. 175\u2013181.","DOI":"10.1109\/FPGA.1997.624617"},{"issue":"8","key":"28_CR2","doi-asserted-by":"crossref","first-page":"850","DOI":"10.1109\/43.856973","volume":"19","author":"P. K. Chan","year":"2000","unstructured":"P. K. Chan, M. Schlag, C. Ebeling and L. McMurchie, \u201cDistributed-Memory Parallel Routing for Field-Programmable Gate Arrays\u201d, IEEE Trans. on CAD, Vol. 19, No. 8,pp. 850\u2013862, August 2000.","journal-title":"IEEE Trans. on CAD"},{"key":"28_CR3","unstructured":"L. A. F. Cabral, J. S. Aude and N. Maculan, \u201cFPGA Routing: A Brief Survey and a Parallel Strategy\u201d, in Proc. Brazilian Symp. of Operational Research, Brazil, pp. 1624\u20131633, October 1999."},{"key":"28_CR4","unstructured":"L. A. F. Cabral, \u201cParalleling Routing Phase of Circuits Based on FPGAs\u201d, Ph.D Thesis, Federal University of Rio de Janeiro, 2001."},{"key":"28_CR5","unstructured":"S. Yang, \u201cLogic Synthesis and Optimization Benchmark, version 3.0\u201d, Tech. Report, MCNC, USA, 1991."},{"key":"28_CR6","doi-asserted-by":"crossref","unstructured":"H. Hsieh, W. Carter, J. Ja, E. Cheung, S. Schreifels, C. Erickson, P. Freidin, L. Tinkey and R. Kanazawa, \u201cThird-Generation Architecture Boosts Speed and density of Field-Programmable Gate Arrays\u201d, Proc. 1990 CICC, May 1990, pp. 31.2.1\u201331.2.7.","DOI":"10.1109\/CICC.1990.124841"},{"issue":"1","key":"28_CR7","doi-asserted-by":"crossref","first-page":"33","DOI":"10.1109\/43.486270","volume":"15","author":"Y.-L. Wu","year":"1996","unstructured":"Y.-L. Wu, S. Tsukiyama, M. Marek-Sadowska, \u201cGraph Based Analysis of FPGA Routing\u201d, IEEE Trans. CAD, 15(1), pp. 33\u201344, January 1996.","journal-title":"IEEE Trans. CAD"},{"issue":"3","key":"28_CR8","doi-asserted-by":"publisher","first-page":"277","DOI":"10.1109\/4.75006","volume":"26","author":"J. Rose","year":"1991","unstructured":"J. Rose and S. Brown, \u201cFlexibility of Interconnection Structures in Field-Programmable Gate Arrays\u201d, IEEE Journal of Solid State Circuits, 26 (3), pp. 277\u2013282, March 1991.","journal-title":"IEEE Journal of Solid State Circuits"},{"key":"28_CR9","doi-asserted-by":"crossref","unstructured":"L. McMurchie and C. Ebeling, \u201cPathfinder: A Negotiation-based Perfomance Driven router for FPGAs\u201d, in Proc. 3 rd Int ACM\/SIGDA Symp. Field-Programmable Gate Arrays, Monterey, CA, Feb. 1995, pp. 111\u2013117.","DOI":"10.1109\/FPGA.1995.242049"},{"key":"28_CR10","doi-asserted-by":"crossref","unstructured":"V. Betz and J. Rose, \u201cVPR: A New Packing, Placement and Routing Tool for FPGA Research\u201d, in 7th Int\u2019l Workshop on Field Programmable Logic and Applic., London, 1997, pp.213\u2013222.","DOI":"10.1007\/3-540-63465-7_226"},{"key":"28_CR11","doi-asserted-by":"crossref","unstructured":"J. Swartz, V. Betz and J. Rose, \u201cA Fast Routability-Driven for FPGA\u201d, in ACM\/SIGDA Int\u2019l Symp. on Field-Programmable Gate Arrays, Monterey, CA, 1998, pp. 140\u2013149.","DOI":"10.1145\/275107.275134"},{"key":"28_CR12","unstructured":"R. Tessier, \u201cNegotiated A* routing for FPGAs\u201d, presented at the Proc. the Fifth Canadian Workshop on Field-Programmable Devices, Quebec, Canada, June, 1998."},{"key":"28_CR13","doi-asserted-by":"crossref","unstructured":"Z. Xing, J. Chandy, and P. Banerjee, \u201c Parallel global routing for standard cell\u201d, in Proc. IPPS-97, Apr. 1997, pp. 527\u2013532.","DOI":"10.1109\/IPPS.1997.580951"},{"key":"28_CR14","unstructured":"M. Snir, S. Otto, S. Huss-Lederman, D. Walker and J. Dongarra, \u201cMPI The Complete Reference\u201d, The MIT Press, 1997."}],"container-title":["Lecture Notes in Computer Science","Field-Programmable Logic and Applications: Reconfigurable Computing Is Going Mainstream"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/3-540-46117-5_28","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,2,19]],"date-time":"2025-02-19T19:21:42Z","timestamp":1739992902000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/3-540-46117-5_28"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2002]]},"ISBN":["9783540441083","9783540461173"],"references-count":14,"URL":"https:\/\/doi.org\/10.1007\/3-540-46117-5_28","relation":{},"ISSN":["0302-9743"],"issn-type":[{"type":"print","value":"0302-9743"}],"subject":[],"published":{"date-parts":[[2002]]}}}