{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T15:40:09Z","timestamp":1725550809154},"publisher-location":"Berlin, Heidelberg","reference-count":15,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540441083"},{"type":"electronic","value":"9783540461173"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2002]]},"DOI":"10.1007\/3-540-46117-5_34","type":"book-chapter","created":{"date-parts":[[2010,3,29]],"date-time":"2010-03-29T21:14:23Z","timestamp":1269897263000},"page":"322-331","source":"Crossref","is-referenced-by-count":1,"title":["A Clocking Technique with Power Savings in Virtex-Based Pipelined Designs"],"prefix":"10.1007","author":[{"given":"Oswaldo","family":"Cadenas","sequence":"first","affiliation":[]},{"given":"Graham","family":"Megson","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2002,8,16]]},"reference":[{"key":"34_CR1","doi-asserted-by":"publisher","first-page":"6","DOI":"10.1109\/7384.928306","volume":"1","author":"L. Benini","year":"2001","unstructured":"L. Benini, G. De Micheli, and E. Macii, \u201cDesigning for Low-power Circuits: Practical Recipes\u201d, IEEE Circuits & Systems Magazine, Vol. 1, No. 1, Q1, 2001, pp. 6\u201325.","journal-title":"IEEE Circuits & Systems Magazine"},{"key":"34_CR2","unstructured":"S. Wenande and R. Chidester, \u201cXilinx Takes Power Analysis to New Levels with Xpower\u201d, Xcell Journal, Issue 41, Xilinx Inc., Fall\/Winter 2001., pp. 26\u201327."},{"key":"34_CR3","volume-title":"Application-specific Integrated Circuits","author":"M. Smith","year":"1997","unstructured":"M. Smith, Application-specific Integrated Circuits, Reading, Mas: Addison-Wesley, 1997."},{"key":"34_CR4","unstructured":"P. Alfke, \u201cEvolution, Revolution and Convolution\u201d, Tutorial at 11th Int. Conf. on Field Programmable Logic and Applications, Belfast, Norhtern Ireland, 2001."},{"issue":"4","key":"34_CR5","doi-asserted-by":"publisher","first-page":"32","DOI":"10.1109\/54.329451","volume":"11","author":"L. Benini","year":"1994","unstructured":"L. Benini, P. Siegel, and G. De Micheli, \u201cAutomatic Synthesis of Gated Clocks for Power Reduction in Sequential Circuits\u201d, IEEE DEsign and Test of Computers, Vol. 11, No. 4, pp.32\u201340, December 1994.","journal-title":"IEEE DEsign and Test of Computers"},{"key":"34_CR6","unstructured":"P. J. Schoenmakers, and J. F. M. Theeuwen, \u201cClock gating on RT-level VHDL\u201d, Proc. of the Int. Workshop on Logic Synthesis, Tahoe City, CA, June 7\u201310, 1998, pp. 387\u2013391."},{"key":"34_CR7","unstructured":"J. Jenkins, \u201cReducing CPLD Power Consupmtion\u201d Xcell Journal, Xilinx Inc., Q4 1998. http:\/\/www.xilinx.com\/apps\/3volt.htm"},{"key":"34_CR8","unstructured":"P. Alfke, \u201cLow Power FPGA Achieves 400 MHz Performance\u201d Xcell Journal, Xilinx Inc., Q2, 1998. http:\/\/www.xilinx.com\/apps\/3volt.htm"},{"key":"34_CR9","doi-asserted-by":"crossref","unstructured":"B. Kumthekar. L. Benini, E. Macii, and F. Somenzi, ldIn-Place Power Optimization for LUT-Based FPGAs\u201d, Proc. of the 31st Design Automation Conference, June 15\u201418, San Francisco, 1998.","DOI":"10.1145\/277044.277224"},{"key":"34_CR10","doi-asserted-by":"crossref","unstructured":"J. Hwang, F. Chiang and T. Hwang, ldA Re-engineering Approach to Low Power FPGA Design Using SPFD\u201d, Proc. of the 31st Design Automation Conference, June 15\u201318, San Francisco, 1998.","DOI":"10.1145\/277044.277225"},{"key":"34_CR11","doi-asserted-by":"crossref","unstructured":"O. Cadenas and G. Megson, \u201cPipelining considerations for an FPGA case\u201d, Proc. of Euromicro Symposium on Digital Systems Design (DSD 2001) Warsaw, Poland, September 4th\u20136th, 2001, pp.276\u2013283.","DOI":"10.1109\/DSD.2001.952298"},{"key":"34_CR12","doi-asserted-by":"crossref","unstructured":"K. Wei\u00df, C. Oetker, I. Katchan, T. Steckstor, and W. Rosentiel Power estimation approach for SRAM-based FPGAs, Proceedings of the 2000 ACM\/SIGDA eighth international symposium on Field programmable gate arrays February 10\u201311, 2000, Monterey, CA USA, pp. 195\u2013202.","DOI":"10.1145\/329166.329207"},{"key":"34_CR13","volume-title":"Introduction to Data Compression","author":"K. Sayood","year":"1996","unstructured":"K. Sayood. Introduction to Data Compression. San Francisco, CA: Morgan Kaufmann Publishers, 1996."},{"issue":"17","key":"34_CR14","doi-asserted-by":"publisher","first-page":"1435","DOI":"10.1049\/el:19970993","volume":"33","author":"G.M. Megson","year":"1997","unstructured":"Megson, G.M. and Diemoz E., 1997. ldScalar Quantisation Using a Fast Systolic Array,\u201d in Electronics Letters, 1997, Vol. 33, No. 17, pp.1435\u20131437.","journal-title":"Electronics Letters"},{"key":"34_CR15","series-title":"Lect Notes Comput Sci","doi-asserted-by":"publisher","first-page":"420","DOI":"10.1007\/3-540-44687-7_43","volume-title":"Field Programmable Logic and Applications, FPL2001","author":"J. O. Cadenas","year":"2001","unstructured":"J. O. Cadenas, G. M. Megson, An n-bit reconfigurable scalar quantiser. Field Programmable Logic and Applications, FPL2001, LNCS 2147, Gordon Brebner and Roger Woods (Eds.) Springer, Belfast, UK. 2001, pp.420\u2013429."}],"container-title":["Lecture Notes in Computer Science","Field-Programmable Logic and Applications: Reconfigurable Computing Is Going Mainstream"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/3-540-46117-5_34","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,5,27]],"date-time":"2019-05-27T19:04:42Z","timestamp":1558983882000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/3-540-46117-5_34"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2002]]},"ISBN":["9783540441083","9783540461173"],"references-count":15,"URL":"https:\/\/doi.org\/10.1007\/3-540-46117-5_34","relation":{},"ISSN":["0302-9743"],"issn-type":[{"type":"print","value":"0302-9743"}],"subject":[],"published":{"date-parts":[[2002]]}}}