{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,1,22]],"date-time":"2025-01-22T05:28:58Z","timestamp":1737523738959,"version":"3.33.0"},"publisher-location":"Berlin, Heidelberg","reference-count":39,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540664833"},{"type":"electronic","value":"9783540482543"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[1999]]},"DOI":"10.1007\/3-540-48254-7_18","type":"book-chapter","created":{"date-parts":[[2007,11,6]],"date-time":"2007-11-06T22:45:26Z","timestamp":1194389126000},"page":"251-266","source":"Crossref","is-referenced-by-count":2,"title":["Design of Totally Self-Checking Code-Disjoint Synchronous Sequential Circuits"],"prefix":"10.1007","author":[{"given":"Jerzy W.","family":"Greblicki","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Stanis\u0142aw J.","family":"Piestrak","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2000,3,24]]},"reference":[{"key":"18_CR1","unstructured":"E. S. Sogomonyan and E. V. Slabakov, Self-Checking Devices and Fault-Tolerant Systems, Radio i Svyaz, Moscow, 1989 (in Russian)."},{"key":"18_CR2","unstructured":"M. Diaz, \u201cDesign of totally self-checking and fail-safe sequential machines,\u201d in Dig. Pap. 4th Int. FTC Symp., Urbana, IL, 1974, pp. 3-19\u20133-24."},{"key":"18_CR3","doi-asserted-by":"publisher","first-page":"276","DOI":"10.1109\/TC.1979.1675338","volume":"C-28","author":"M. Diaz","year":"1979","unstructured":"M. Diaz et al., \u201cUnified design of self-checking and fail-safe combinational circuits and sequential machines,\u201d IEEE Trans. Comput., vol. C-28, pp. 276\u2013281, March 1979.","journal-title":"IEEE Trans. Comput."},{"key":"18_CR4","unstructured":"F. \u00d6zg\u00fcner, \u201cDesign of totally self-checking asynchronous and synchronous sequential machines,\u201d in Dig. Pap. 7th Int. FTC Symp., June 1977, pp. 124\u2013129."},{"issue":"6","key":"18_CR5","first-page":"913","volume":"38","author":"V. I. Maznev","year":"1977","unstructured":"V. I. Maznev, \u201cSynthesis of totally self-checking sequential circuits,\u201d Autom. Remote Control, vol. 38, pp. 913\u2013920, No. 6, 1977.","journal-title":"Autom. Remote Control"},{"issue":"3","key":"18_CR6","first-page":"6","volume":"11","author":"V. V. Sapozhnikov","year":"1977","unstructured":"V. V. Sapozhnikov, Vl. V. Sapozhnikov, and V. G. Trokhov, \u201cDesign of self-checking sequential networks,\u201d Avtom. Vychisl. Tekh., vol. 11, pp. 6\u201311, No. 3, 1977.","journal-title":"Avtom. Vychisl. Tekh."},{"key":"18_CR7","first-page":"271","volume":"4","author":"R. David","year":"1978","unstructured":"R. David and P. Thevenod-Fosse, \u201cDesign of totally self-checking asynchronous modular circuits,\u201d J. Des. Autom. Fault-Tolerant Comput., vol. 4, pp. 271\u2013287, Oct. 1978.","journal-title":"J. Des. Autom. Fault-Tolerant Comput."},{"issue":"1","key":"18_CR8","first-page":"124","volume":"40","author":"V. V. Sapozhnikov","year":"1979","unstructured":"V. V. Sapozhnikov and Vl. V. Sapozhnikov, \u201cSynthesis of totally self-checking asynchronous automata,\u201d Autom. Remote Control, vol. 40, pp. 124\u2013133, No. 1, 1979.","journal-title":"Autom. Remote Control"},{"key":"18_CR9","unstructured":"V. V. Sapozhnikov and Vl. V. Sapozhnikov, Discrete Automata with Error Detection, Energoatomizdat, Leningrad, SU, 1984 (in Russian)."},{"key":"18_CR10","doi-asserted-by":"crossref","first-page":"1121","DOI":"10.1109\/TC.1987.5009545","volume":"C-36","author":"T. Nanya","year":"1987","unstructured":"T. Nanya and T. Kawamura, \u201cA note on strongly fault secure sequential circuits,\u201d IEEE Trans. Comput., vol. C-36, pp. 1121\u20131123, Sept. 1987.","journal-title":"IEEE Trans. Comput."},{"key":"18_CR11","first-page":"878887","volume":"12","author":"N. K. Jha","year":"1993","unstructured":"N. K. Jha and S.-J. Wang, \u201cDesign and synthesis of self-checking VLSI circuits,\u201d IEEE Trans. Comp.-Aided Des., vol. 12, pp. 878887, June 1993.","journal-title":"IEEE Trans. Comp.-Aided Des."},{"key":"18_CR12","first-page":"4954","volume":"142","author":"C.-S. Lai","year":"1995","unstructured":"C.-S. Lai and C.-L. Wey, \u201cSOLiT: an automated system for synthesising reliable sequential circuits with multilevel logic implementation,\u201d IEE Proc.-Comput. Digit. Tech., vol. 142, pp. 4954, Jan. 1995.","journal-title":"IEE Proc.-Comput. Digit. Tech."},{"issue":"6","key":"18_CR13","first-page":"984","volume":"36","author":"V. V. Danilov","year":"1975","unstructured":"V. V. Danilov et al., \u201cAn algebraic model for the hardware monitoring of automata,\u201d Autom. Remote Control, vol. 36, pp. 984\u2013981, No. 6, 1975.","journal-title":"Autom. Remote Control"},{"key":"18_CR14","unstructured":"J. Viaud and R. David, \u201cSequentially self-checking circuits,\u201d in Dig. Pap. 10th Int. FTC Symp., Kyoto, Japan, Oct. 1980, pp. 263\u2013268."},{"key":"18_CR15","unstructured":"N. S. Shcherbakov and B. P. Podkopaev, Structural Theory of Hardware Checking of Digital Devices, Mashinostroenie, Moscow, 1982 (in Russian)."},{"issue":"3","key":"18_CR16","doi-asserted-by":"publisher","first-page":"24","DOI":"10.1109\/MDT.1995.466370","volume":"12","author":"R. A. Parekhji","year":"1995","unstructured":"R. A. Parekhji, G. Venkatesh, and S. D. Sherlekar, \u201cConcurrent error detection using monitoring machines,\u201d IEEE Design and Test of Computers, vol. 12, No. 3, pp. 24\u201332, Fall 1995.","journal-title":"IEEE Design and Test of Computers"},{"key":"18_CR17","doi-asserted-by":"publisher","first-page":"68","DOI":"10.1016\/S0019-9958(61)80037-5","volume":"4","author":"J. M. Berger","year":"1961","unstructured":"J. M. Berger, \u201cA note on error detection codes for asymmetric binary channels,\u201d Inform. Contr., vol. 4, pp. 68\u201373, Mar. 1961.","journal-title":"Inform. Contr."},{"key":"18_CR18","doi-asserted-by":"publisher","first-page":"64","DOI":"10.1016\/S0019-9958(62)90223-1","volume":"5","author":"C. V. Freiman","year":"1962","unstructured":"C. V. Freiman, \u201cOptimal error detection codes for completely asymmetric binary channels,\u201d Inform. Contr., vol. 5, pp. 64\u201371, Mar. 1962.","journal-title":"Inform. Contr."},{"key":"18_CR19","first-page":"321","volume":"2","author":"J. E. Smith","year":"1977","unstructured":"J. E. Smith, \u201cThe design of totally self-checking check circuits for a class of un-ordered codes,\u201d J. Des. Autom. Fault-Tolerant Comput., vol. 2, pp. 321\u2013342, Oct. 1977.","journal-title":"J. Des. Autom. Fault-Tolerant Comput."},{"key":"18_CR20","unstructured":"G. P. Mak, J. A. Abraham, and E. S. Davidson, \u201cThe design of PLAs with concurrent error detection,\u201d in Dig. Pap. 12th Int. FTC Symp., Santa Monica, CA, June 1982, pp. 303\u2013310."},{"key":"18_CR21","doi-asserted-by":"crossref","first-page":"741","DOI":"10.1109\/TC.1984.5009361","volume":"C-33","author":"J. E. Smith","year":"1984","unstructured":"J. E. Smith, \u201cOn separable unordered codes,\u201d IEEE Trans. Comput., vol. C-33, pp. 741\u2013743, Aug. 1984.","journal-title":"IEEE Trans. Comput."},{"key":"18_CR22","doi-asserted-by":"crossref","unstructured":"S. J. Piestrak, \u201cDesign of TSC code-disjoint inverter-free PLA\u2019s for separable un-ordered codes,\u201d in Proc. ICCD\u201994, Int. Conf. on Computer Design: VLSI in Com-puters & Processors, Cambridge, MA, Oct. 10-12, 1994, pp. 128\u2013131.","DOI":"10.1109\/ICCD.1994.331871"},{"key":"18_CR23","unstructured":"W. C. Carter and P. R. Schneider, \u201cDesign of dynamically checked computers,\u201d in Proc. IFIP Conf., Edinburgh, Scotland, Aug. 1968, pp. 878\u2013883."},{"key":"18_CR24","unstructured":"S. J. Piestrak, Design of Self-Testing Checkers for Unidirectional Error Detecting Codes, Scientific Papers of Inst. of Techn. Cybern. of Techn. Univ. of Wroc law, No. 92, Ser.: Monographs No. 24, Oficyna Wyd. Polit. Wroc l., Wroc law 1995, 112 pp."},{"issue":"4","key":"18_CR25","first-page":"247","volume":"5","author":"S. J. Piestrak","year":"1997","unstructured":"S. J. Piestrak, \u201cDesign of encoders and self-testing checkers for some systematic unidirectional error detecting codes,\u201d J. of Microelectronic Systems Integration, Sp. Issue on Defect and Fault Tolerance in VLSI Systems, vol. 5, pp. 247\u2013260, No. 4, 1997.","journal-title":"J. of Microelectronic Systems Integration"},{"key":"18_CR26","unstructured":"J. F. Wakerly, Error Detecting Codes, Self-Checking Circuits and Applications, North-Holland, New York, 1978."},{"key":"18_CR27","unstructured":"M. A. Marouf and A. D. Friedman, \u201cDesign of self-checking checkers for Berger codes,\u201d in Dig. Pap. 8th Int. FTC Symp., Toulouse, France, June 1978, pp. 179\u2013184."},{"key":"18_CR28","doi-asserted-by":"publisher","first-page":"753","DOI":"10.1109\/TC.1984.5009365","volume":"C-33","author":"J. Khakbaz","year":"1984","unstructured":"J. Khakbaz and E. J. McCluskey, \u201cSelf-testing embedded parity checkers,\u201d IEEE Trans. Comput., vol. C-33, pp. 753\u2013756, Aug. 1984.","journal-title":"IEEE Trans. Comput."},{"key":"18_CR29","doi-asserted-by":"publisher","first-page":"382","DOI":"10.1049\/el:19910241","volume":"27","author":"F. \u00d6zg\u00fcner","year":"1991","unstructured":"F. \u00d6zg\u00fcner, \u201cDesign of totally self-checking embedded two-rail code checkers,\u201d Electr. Lett., vol. 27, pp. 382\u2013384, 14th Feb. 1991.","journal-title":"Electr. Lett."},{"key":"18_CR30","unstructured":"S. J. Piestrak, \u201cDesign method of combinational self-testing checkers for a class of incomplete 2-rail codes,\u201d submitted to IEEE Trans. Comput."},{"issue":"3","key":"18_CR31","first-page":"234240","volume":"18","author":"V. Rabara","year":"1981","unstructured":"V. Rabara, \u201cDesign of self-checking checker for 1-out-of-n code (n > 3), \u201d in Proc. 4th Int. Conf. on Fault-Tolerant Syst. Diagnostics, Brno, Czechoslovakia, Sept. 28-30, 1981, pp. 234240; also appears as: V. V. Sapozhnikov and V. Rabara, \u201cUniversal synthesis algorithm for 1=n testers, \u201d Probl. Inf. Transm., vol. 18, pp. 209218, No. 3, 1982.","journal-title":"Proc. 4th Int. Conf. on Fault-Tolerant Syst. Diagnostics, Brno, Czechoslovakia, Sept. 28-30"},{"key":"18_CR32","doi-asserted-by":"publisher","first-page":"263","DOI":"10.1109\/T-C.1973.223705","volume":"C-22","author":"D. A. Anderson","year":"1973","unstructured":"D. A. Anderson and G. Metze, \u201cDesign of totally self-checking check circuits for m-out-of-n codes,\u201d IEEE Trans. Comput., vol. C-22, pp. 263\u2013269, Mar. 1973.","journal-title":"IEEE Trans. Comput."},{"key":"18_CR33","unstructured":"S. J. Piestrak, \u201cDesign method of self-testing checkers for 1-out-of-n codes, \u201d in Proc. 6th Int. Conf. on Fault-Tolerant Syst. Diagnostics, Brno, Czechoslovakia, Sept. 1983, pp. 57\u201363."},{"key":"18_CR34","unstructured":"S. J. Piestrak, \u201cDesign method of totally self-checking checkers for m-out-of-n codes, \u201d in Dig. Pap. 13th Int. FTC Symp., June 28-30, 1983, Milan, Italy, pp. 162\u2013168."},{"key":"18_CR35","doi-asserted-by":"crossref","unstructured":"S. J. Piestrak, \u201cThe minimal test set for sorting networks and the use of sorting networks in self-testing checkers for unordered codes,\u201d in Dig. Pap. 20th Int. FTC Symp., Newcastle upon Tyne, UK, June 1990, pp. 457\u2013464.","DOI":"10.1109\/FTCS.1990.89382"},{"key":"18_CR36","unstructured":"S. J. Piestrak, \u201cGeneral design procedure of self-testing checkers for all m-out-of-n codes with m \u2265 3 using parallel counters,\u201d in Proc. 4th IEEE Int. On-Line Testing Workshop, July 7-9, 1998, Capri, Italy, pp. 182\u2013186."},{"key":"18_CR37","unstructured":"S. J. Piestrak, \u201cPLA implementation of totally self-checking circuits using m-out-of-n codes,\u201d in Proc. ICCD\u201985, Port Chester, N.Y., Oct. 1-3, 1985, pp. 777\u2013781."},{"key":"18_CR38","doi-asserted-by":"publisher","first-page":"360","DOI":"10.1109\/12.48866","volume":"C-39","author":"S. J. Piestrak","year":"1990","unstructured":"S. J. Piestrak, \u201cDesign of high-speed and cost-effective self-testing checkers for low-cost arithmetic codes,\u201d IEEE Trans. Comput., vol. C-39, pp. 360\u2013374, March 1990.","journal-title":"IEEE Trans. Comput."},{"key":"18_CR39","doi-asserted-by":"crossref","unstructured":"S. J. Piestrak, \u201cGeneral design principles of self-testing code-disjoint PLA\u2019s,\u201d Proc. ATS\u201993 \u2014 2nd Asian Test Symp., Beijing, China, Nov. 18-19, 1993, pp. 287\u2013292.","DOI":"10.1109\/ATS.1993.398819"}],"container-title":["Lecture Notes in Computer Science","Dependable Computing \u2014 EDCC-3"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/3-540-48254-7_18","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,1,22]],"date-time":"2025-01-22T03:59:05Z","timestamp":1737518345000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/3-540-48254-7_18"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1999]]},"ISBN":["9783540664833","9783540482543"],"references-count":39,"URL":"https:\/\/doi.org\/10.1007\/3-540-48254-7_18","relation":{},"ISSN":["0302-9743"],"issn-type":[{"type":"print","value":"0302-9743"}],"subject":[],"published":{"date-parts":[[1999]]}}}