{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T23:31:26Z","timestamp":1725492686321},"publisher-location":"Berlin, Heidelberg","reference-count":21,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540660934"},{"type":"electronic","value":"9783540487531"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[1999]]},"DOI":"10.1007\/3-540-48753-0_32","type":"book-chapter","created":{"date-parts":[[2007,10,10]],"date-time":"2007-10-10T09:58:29Z","timestamp":1192010309000},"page":"371-384","source":"Crossref","is-referenced-by-count":0,"title":["System on Chip Specification and Design Languages Standardization"],"prefix":"10.1007","author":[{"given":"Jean","family":"Mermet","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2002,6,11]]},"reference":[{"key":"32_CR1","doi-asserted-by":"crossref","unstructured":"J.R. ABrial \u00abThe B-book. Assigning programs to meanings\u00bb, Cambridge university press, 1996.","DOI":"10.1017\/CBO9780511624162"},{"key":"32_CR2","unstructured":"M. Barbacci, D. Borrione, D. Dietmeyer, F. Hill, R. Piloty, P. Skelly: \u00abCONLAN Report\u00bb, Lect. notes in Computer Science No 151, Springer 00BBerlag, 1983"},{"key":"32_CR3","unstructured":"David L. Barton \u00abSystems Level Design Section of the Industry Standards Roadmap\u00bb The systems Level Description Language Committee"},{"key":"32_CR4","doi-asserted-by":"crossref","unstructured":"G.V. Bochman, Specification Languages for Communication Protocols, Proceedings of the Confernece on Hardware Description Languages, April 1993","DOI":"10.1016\/B978-0-444-81641-2.50035-6"},{"key":"32_CR5","doi-asserted-by":"crossref","unstructured":"D. Biorrione: \u00abCASCADE\u00bb, in \u00abFundamentals and Standards in Hardware Description Languages\u00bb KLUWER ACADEMIC, (1993).","DOI":"10.1007\/978-94-011-1914-6_14"},{"key":"32_CR6","doi-asserted-by":"crossref","unstructured":"R.T. Boute \u00abFundamentals of Hardware Description Languages and Declarative Languages\u00bb in \u00abFundamentals and Standars in Hardware Description Languages\u00bb KLUWER ACADEMIC, (1993)","DOI":"10.1007\/978-94-011-1914-6_1"},{"key":"32_CR7","unstructured":"R. Braek, SDL Basics, S intef Delab"},{"key":"32_CR8","unstructured":"K. Buchenrieder, A. Pyteel and C. Veith, Mapping StateCharts Models onto an FPGA Based ASIP Architecture, Proc. of EuroDAC with Euro-VHDL, September 1996"},{"key":"32_CR9","unstructured":"\u00abCONLAN: a short review and critical comparison with VHDL\u00bb IEEE Design & Test of computers. Sept 1992"},{"key":"32_CR10","doi-asserted-by":"crossref","unstructured":"J.M. Daveau, G. Fernandex Marchioro, C. Alberto Valderrama and A. Jerraya, VHDL generation from SDL specifications, IFIP 1997. Chapman & Hall","DOI":"10.1007\/978-0-387-35064-6_18"},{"key":"32_CR11","doi-asserted-by":"publisher","first-page":"198","DOI":"10.1147\/sj.32.0198","volume":"3","author":"A.D. Falkoff","year":"1964","unstructured":"Falkoff, A.D., Iverson, K.E., Sussenguth, E.H.: \u201cFormal description of system\/360\u201d IBM sys. J. vol. 3, pp 198\u2013262, 1964.","journal-title":"IBM sys. J."},{"key":"32_CR12","doi-asserted-by":"crossref","unstructured":"W. Glunz, T. Kruse, T. Rossel and D. Monjeau, Integrating SDL and VHDL for System Level Specification, Proceedings of the Conference on Hardware Description Languages, April 1993","DOI":"10.1016\/B978-0-444-81641-2.50021-6"},{"key":"32_CR13","doi-asserted-by":"crossref","unstructured":"D. Harel: Statecharts: A visual formalism for com-plex systems. Science of Computer Programming, 8, 1987","DOI":"10.1016\/0167-6423(87)90035-9"},{"key":"32_CR14","doi-asserted-by":"crossref","unstructured":"A. Jerraya, J. Mermeteditors. \u201cSystem level synthesis\u201d KLUWER ACADEMIC. Spring 1999.","DOI":"10.1007\/978-94-011-4698-2"},{"key":"32_CR15","doi-asserted-by":"crossref","unstructured":"E. Lee and A. Sangiovanni-Vincentelli, A Framework For Comparing Models Of Computation, IEEE Transactions on CAD, September 1998.","DOI":"10.1109\/43.736561"},{"key":"32_CR16","unstructured":"Modelica Version 1.1-December 1998, Modelica Tutorial and Design Rationale, (HTML format)(Portable Document Format), updated (Modelica 1.1)"},{"key":"32_CR17","unstructured":"O. Pulkkinen and K. Kr\u00f6nlof, Integration of SDL and VHDL for High Level Digital Design, Proc. of EuroDAC with Euro-VHDL, September 1992."},{"key":"32_CR18","doi-asserted-by":"crossref","unstructured":"Franz J. Ramming, \u00abSystem Level Design\u00bb, in \u00abFundamentals and Standards in Hardware Description Languges\u00bb KLUWER, (1993)","DOI":"10.1007\/978-94-011-1914-6_4"},{"key":"32_CR19","unstructured":"A. Sarma, Intro. to SDL-92, EURESCOM, G"},{"key":"32_CR20","unstructured":"VHDL modeling terminology and taxonomy, RASSP doc, Sept 9, 1996"},{"key":"32_CR21","unstructured":"E. Villar, Berrojo L, Sanchez P: \u00abHigh-level synthesis and simulation with VHDL\u00bb, Proc. of 2nd EuroVHDL Conf, Sockholm, Sept. 8\u201311, 1991"}],"container-title":["Lecture Notes in Computer Science","Reliable Software Technologies \u2014 Ada-Europe\u2019 99"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/3-540-48753-0_32","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,5,3]],"date-time":"2019-05-03T13:59:10Z","timestamp":1556891950000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/3-540-48753-0_32"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1999]]},"ISBN":["9783540660934","9783540487531"],"references-count":21,"URL":"https:\/\/doi.org\/10.1007\/3-540-48753-0_32","relation":{},"ISSN":["0302-9743"],"issn-type":[{"type":"print","value":"0302-9743"}],"subject":[],"published":{"date-parts":[[1999]]}}}