{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,6]],"date-time":"2025-06-06T10:25:56Z","timestamp":1749205556819,"version":"3.40.2"},"publisher-location":"Berlin, Heidelberg","reference-count":11,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540584261"},{"type":"electronic","value":"9783540487852"}],"license":[{"start":{"date-parts":[[1994,1,1]],"date-time":"1994-01-01T00:00:00Z","timestamp":757382400000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[1994]]},"DOI":"10.1007\/3-540-58426-9_130","type":"book-chapter","created":{"date-parts":[[2012,2,26]],"date-time":"2012-02-26T15:59:13Z","timestamp":1330271953000},"page":"165-177","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":4,"title":["The Configuration Ratio: A model for simulating CMOS intra-gate bridge with variable logic thresholds"],"prefix":"10.1007","author":[{"given":"M.","family":"Renovell","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"P.","family":"Huc","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Y.","family":"Bertrand","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2005,6,7]]},"reference":[{"key":"10_CR1","doi-asserted-by":"crossref","unstructured":"W. Maly, \u201dRealistic Fault Modeling for VLSI Testing\u201d, in Proceeding of Design Automation Conference, pp. 173\u2013180, 1987.","DOI":"10.1145\/37888.37914"},{"key":"10_CR2","doi-asserted-by":"crossref","first-page":"1181","DOI":"10.1109\/43.9188","volume":"7","author":"F. J. Ferguson","year":"1988","unstructured":"F. J. Ferguson and J. P. Shen, \u201dA CMOS Fault Extractor for Inductive Fault Analysis\u201d, IEEE Transactions on CAD, vol. 7, pp. 1181\u20131194, Nov. 1988.","journal-title":"IEEE Transactions on CAD"},{"key":"10_CR3","doi-asserted-by":"crossref","unstructured":"J. M. Soden and C. F. Hawkins, \u201dElectrical Properties and Detection Methods for CMOS ICs Defects\u201d, in Proc. of IEEE European Test Conference, pp. 159\u2013167, 1989.","DOI":"10.1109\/ETC.1989.36238"},{"key":"10_CR4","doi-asserted-by":"crossref","unstructured":"S.D. Millman and J. McCluskey, \u201dDetecting Bridging Faults With Stuck-at Test Sets\u201d, Proc. Int. Test Conf, pp. 773\u2013783, Washington, DC, USA, Sept. 12\u201314, 1988.","DOI":"10.1109\/TEST.1988.207864"},{"key":"10_CR5","doi-asserted-by":"publisher","first-page":"211","DOI":"10.1109\/41.19071","volume":"36","author":"C.F. Hawkins","year":"1989","unstructured":"C.F. Hawkins, J.M. Soden, R.R. Fritzemeier & L.K. Horning, \u201dQuiescent Power Supply Current Measurement for CMOS IC Defect Detection\u201d, IEEE Trans. on Industrial Electronics, 36, pp. 211\u2013218, May, 1989.","journal-title":"IEEE Trans. on Industrial Electronics"},{"key":"10_CR6","doi-asserted-by":"crossref","unstructured":"T. Storey & W. Maly, \u201dCMOS Bridging Fault Detection\u201d, Proc. Int. Test Conf., pp. 842\u2013851, 1990.","DOI":"10.1109\/TEST.1990.114102"},{"key":"10_CR7","doi-asserted-by":"crossref","unstructured":"R.C. Aitken, \u201dA Comparison of Defect Models for Fault Location with Iddq Measurements\u201d, Proc. Int. Test Conf., pp. 778\u2013787, 1992.","DOI":"10.1109\/TEST.1992.527900"},{"key":"10_CR8","doi-asserted-by":"crossref","unstructured":"M. Dalpasso, M. Favalli, P. Olivo, B. Ricco, \u201dParametric Bridging Fault Characterization for the Fault Simulation of Library-Based ICs\u201d, Proc. Int. Test Conf., pp. 486\u2013495, 1992.","DOI":"10.1109\/TEST.1992.527860"},{"key":"10_CR9","doi-asserted-by":"crossref","unstructured":"P.C. Maxwell and R.C. Aitken, \u201dBiased Voting: A Method for Simulating CMOS Bridging Faults in the Presence of Variable Gate logic Threshold\u201d, Proc. Int. Test Conf., pp. 63\u201372, 1993.","DOI":"10.1109\/TEST.1993.470717"},{"key":"10_CR10","doi-asserted-by":"crossref","unstructured":"J.J.T. Sousa, EM. Gon\u00c7alves, J.P. Teixeira, \u201d IC Defects-Based Testability Analysis\u201d, Proc. Int. Test Conf, pp. 500\u2013509, Nashville, TN, USA, Oct. 26\u201330, 1991.","DOI":"10.1109\/TEST.1991.519712"},{"key":"10_CR11","doi-asserted-by":"crossref","unstructured":"F.J. Ferguson & J.P. Shen, \u201dExtraction and Simulation of Realistic CMOS Faults Using Inductive Fault Analysis\u201d, Proc. Int. Test Conf., pp. 475\u2013484.","DOI":"10.1109\/TEST.1988.207759"}],"container-title":["Lecture Notes in Computer Science","Dependable Computing \u2014 EDCC-1"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/3-540-58426-9_130","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,3,21]],"date-time":"2025-03-21T22:28:09Z","timestamp":1742596089000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/3-540-58426-9_130"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1994]]},"ISBN":["9783540584261","9783540487852"],"references-count":11,"URL":"https:\/\/doi.org\/10.1007\/3-540-58426-9_130","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[1994]]},"assertion":[{"value":"7 June 2005","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}}]}}