{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,6]],"date-time":"2024-09-06T23:21:44Z","timestamp":1725664904349},"publisher-location":"Berlin, Heidelberg","reference-count":18,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540602750"},{"type":"electronic","value":"9783540447849"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[1995]]},"DOI":"10.1007\/3-540-60275-5_71","type":"book-chapter","created":{"date-parts":[[2012,2,26]],"date-time":"2012-02-26T18:05:55Z","timestamp":1330279555000},"page":"277-292","source":"Crossref","is-referenced-by-count":4,"title":["Deep embedding VHDL"],"prefix":"10.1007","author":[{"given":"Ralf","family":"Reetz","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2005,6,2]]},"reference":[{"unstructured":"ANSI\/IEEE Std 1076-1993. IEEE Standard VHDL Language Reference Manual. IEEE, New York, USA, June 1994.","key":"19_CR1"},{"key":"19_CR2","series-title":"volume 307 of The Kluwer international series in engineering and computer science","volume-title":"Formal Semantics for VHDL","year":"1995","unstructured":"C.D. Kloos and P.T. Breuer, editors. Formal Semantics for VHDL, volume 307 of The Kluwer international series in engineering and computer science. Kluwer, Madrid, Spain, March 1995."},{"doi-asserted-by":"crossref","unstructured":"D. Kapur and H. Zhang. RRL: a rewrite rule laboratory. In Lusk and Overbeek, editors, 9th International Conference on Automated Deduction, pages 768\u2013769. Springer Verlag, 1988.","key":"19_CR3","DOI":"10.1007\/BFb0012889"},{"key":"19_CR4","series-title":"volume 307 of The Kluwer international series in engineering and computer science","volume-title":"Formal Semantics for VHDL","author":"E. B\u00f6rger","year":"1995","unstructured":"E. B\u00f6rger, U. Gl\u00e4sser, and W. M\u00fcller. A formal definition of an abstract VHDL'93 simulator by EA-machines. In C.D. Kloos and P.T. Breuer [2], chapter 4."},{"key":"19_CR5","series-title":"volume 307 of The Kluwer international series in engineering and computer science","volume-title":"Formal Semantics for VHDL","author":"G. Dohmen","year":"1995","unstructured":"G. Dohmen and R. Herrmann. A deterministic finite-state model for VHDL. In C.D. Kloos and P.T. Breuer [2]C.D. Kloos and P.T. Breuer, editors. Formal Semantics for VHDL, volume 307 of The Kluwer international series in engineering and computer science. Kluwer, Madrid, Spain, March 1995, chapter 6."},{"unstructured":"J.P. Van Tassel. A formalisation of the VHDL simulation cycle. In International Workshop on Higher Order Logic Theorem Proving and its Applications, pages 213\u2013228. IFIP WG 10.2, September 1992.","key":"19_CR6"},{"key":"19_CR7","series-title":"volume 307 of The Kluwer international series in engineering and computer science","volume-title":"Formal Semantics for VHDL","author":"M. Fuchs","year":"1995","unstructured":"M. Fuchs and M.Mendler. A functional semantics for delta-delay VHDL based on Focus. In C.D. Kloos and P.T. Breuer C.D. Kloos and P.T. Breuer, editors. Formal Semantics for VHDL, volume 307 of The Kluwer international series in engineering and computer science. Kluwer, Madrid, Spain, March 1995, chapter 1."},{"key":"19_CR8","volume-title":"Technical Report 146","author":"T.F. Melham","year":"1988","unstructured":"T.F. Melham. Automating recursive type definitions in higher order logic. Technical Report 146, University of Cambridge, Computer Laboratory, Cambridge CB2 3QG, England, September 1988."},{"key":"19_CR9","series-title":"volume 307 of The Kluwer international series in engineering and computer science","volume-title":"Formal Semantics for VHDL","author":"P.T. Breuer","year":"1995","unstructured":"P.T. Breuer, L.S. Fernandez, and C.D. Kloos. A functional semantics for unit-delay VHDL. In C.D. Kloos and P.T. Breuer [2], chapter 2."},{"unstructured":"R. Boulton, A. Gordon, M.J.C. Gordon, J. Herbert, J. Harrison, and J. van Tassel. Experience with embedding hardware description languages in HOL. In Proc. of the International Conference on Theorem Provers in Circuit Design: Theory, Practice and Experience, pages 129\u2013156, Nijmegen, June 1992.","key":"19_CR10"},{"unstructured":"R. Herrmann and H. Pargmann. Computing Binary Decision Diagrams for VHDL Data Types. In Proc. European Design Automation Conference (EURO-DAC94), pages 578\u2013585, Grenoble, France, September 1994.","key":"19_CR11"},{"key":"19_CR12","first-page":"378","volume-title":"Lecture Notes in Computer Science No. 859","author":"R. Reetz","year":"1994","unstructured":"R. Reetz and T. Kropf. Simplifying Deep Embedding: A Formalised Code Generator. In T.F. Melham and J. Camilleri, editors, International Workshop on Higher Order Logic Theorem Proving and its Applications, pages 378\u2013390, Malta, September 1994. Lecture Notes in Computer Science No. 859, Springer."},{"key":"19_CR13","series-title":"volume 307 of The Kluwer international series in engineering and computer science","volume-title":"Formal Semantics for VHDL","author":"R. Reetz","year":"1995","unstructured":"R. Reetz and T. Kropf. A flowgraph semantics of VHDL: a basis for hardware verification with VHDL. In C.D. Kloos and P.T. Breuer [2], chapter 7."},{"doi-asserted-by":"crossref","unstructured":"R. Reetz and Th. Kropf. A flowgraph semantics of VHDL: Toward a VHDL verification workbench in HOL. Formal Methods in System Design, 1995. (to appear).","key":"19_CR14","DOI":"10.1007\/BF01383874"},{"key":"19_CR15","volume-title":"Specification and Validation Methods","author":"D.M. Russinoff","year":"1994","unstructured":"D.M. Russinoff. Specification and verification of gate-level VHDL models of synchronous and asynchronous circuits. In E. B\u00f6rger, editor, Specification and Validation Methods. Oxford University Press, Oxford, 1994."},{"key":"19_CR16","series-title":"volume 307 of The Kluwer international series in engineering and computer science","volume-title":"Formal Semantics for VHDL","author":"S. Olcoz","year":"1995","unstructured":"S. Olcoz. A formal model of VHDL using coloured petri nets. In C.D. Kloos and P.T. Breuer [2], chapter 5."},{"doi-asserted-by":"crossref","unstructured":"T.F. Melham. Abstraction mechanisms for hardware verification. In G. Birtwistle and P.A. Subrahmanyam, editors, VLSI Specification, Verification, and Synthesis, pages 129\u2013157. Kluwer Academic Publishers, 1988.","key":"19_CR17","DOI":"10.1007\/978-1-4613-2007-4_9"},{"unstructured":"H. Zima. Compilerbau I, volume 36 of Reihe Informatik. B.I.-Wissenschaftsverlag, 1983.","key":"19_CR18"}],"container-title":["Lecture Notes in Computer Science","Higher Order Logic Theorem Proving and Its Applications"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/3-540-60275-5_71.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,4,28]],"date-time":"2021-04-28T01:35:37Z","timestamp":1619573737000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/3-540-60275-5_71"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1995]]},"ISBN":["9783540602750","9783540447849"],"references-count":18,"URL":"https:\/\/doi.org\/10.1007\/3-540-60275-5_71","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[1995]]}}}