{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,21]],"date-time":"2025-03-21T23:40:08Z","timestamp":1742600408947,"version":"3.40.2"},"publisher-location":"Berlin, Heidelberg","reference-count":10,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540602941"},{"type":"electronic","value":"9783540447863"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[1995]]},"DOI":"10.1007\/3-540-60294-1_107","type":"book-chapter","created":{"date-parts":[[2012,2,26]],"date-time":"2012-02-26T18:07:35Z","timestamp":1330279655000},"page":"139-148","source":"Crossref","is-referenced-by-count":2,"title":["Delay minimal mapping of RTL structures onto LUT based FPGAs"],"prefix":"10.1007","author":[{"given":"A. R.","family":"Naseer","sequence":"first","affiliation":[]},{"given":"M.","family":"Balakrishnan","sequence":"additional","affiliation":[]},{"given":"Anshul","family":"Kumar","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2005,6,2]]},"reference":[{"key":"15_CR1","doi-asserted-by":"crossref","unstructured":"A. R. Naseer, M. Balakrishnan and Anshul Kumar, FAST: FPGA targeted RTL structure Synthesis Technique, Proc. IEEE\/ACM 7th Int. Conf. on VLSI Design'94 January 1994, pp. 21\u201324","DOI":"10.1109\/ICVD.1994.282636"},{"key":"15_CR2","unstructured":"A. R. Naseer, M. Balakrishnan and Anshul Kumar, A technique for synthesizing Data Part using FPGAs, Proc. IEEE\/ACM\/SIGDA 2nd Int. Workshop on Field Programmable Gate Arrays, Berkeley, February 1994."},{"key":"15_CR3","first-page":"99","volume-title":"Lecture Series in Computer Science","author":"A. R. Naseer","year":"1994","unstructured":"A. R. Naseer, M. Balakrishnan and Anshul Kumar, An efficient technique for Mapping RTL structures onto FPGAs, Proc. 4th Int. Workshop on Field Programmable Logic and Applications, Prague, September 1994, Lecture Series in Computer Science, Springer Verlag, vol. 849, pp 99\u2013110."},{"key":"15_CR4","volume-title":"Fachbereich Informatik Technical Report No. 574","author":"M. Balakrishnan","year":"1995","unstructured":"M. Balakrishnan, A. R. Naseer and Anshul Kumar,Optimal Clock Period for synthesized Data Paths, Fachbereich Informatik Technical Report No. 574, University of Dortmund, Germany, April, 1995."},{"key":"15_CR5","doi-asserted-by":"crossref","unstructured":"R. J. Francis, J. Rose, Z. Vranesic, Technology Mapping of Look-up Table- Based FPGAs for performance, Proc. Int. Conf. on CAD, 1991, pp.568\u2013571.","DOI":"10.1109\/ICCAD.1991.185334"},{"key":"15_CR6","doi-asserted-by":"crossref","unstructured":"R. Murgai et al., Performance-Directed Synthesis for Table Look-up Programmable Gate Arrays, Proc. Int. Conf. on CAD, 1991, pp. 572\u2013575.","DOI":"10.1109\/ICCAD.1991.185335"},{"issue":"No.1","key":"15_CR7","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1109\/43.273754","volume":"13","author":"J. Cong","year":"1994","unstructured":"J. Cong and Y. Deng, FlowMap: An optimal Technology Mapping algorithm for Delay Optimization in LookUp-Table based FPGA designs, IEEE Trans. in CAD, vol. 13, No. 1, January 1994, pp. 1\u201312.","journal-title":"IEEE Trans. in CAD"},{"key":"15_CR8","doi-asserted-by":"crossref","unstructured":"M. V. Rao, M. Balakrishnan and Anshul Kumar, \u201dDESSERT: Design Space Exploration of RT Level Components\u201d, Proc. IEEE\/ACM 6th Int. Conf. on VLSI Design'93, January 1993, pp. 299\u2013303.","DOI":"10.1109\/ICVD.1993.669700"},{"key":"15_CR9","doi-asserted-by":"crossref","unstructured":"Anshul Kumar et al. \u201dIDEAS: A Tool for VLSI CAD\u201d, IEEE Design and Test, 1989, pp.50\u201357.","DOI":"10.1109\/54.43079"},{"key":"15_CR10","unstructured":"Xilinx Programmable Gate Array Users' Guide, 1994 Xilinx, Inc."}],"container-title":["Lecture Notes in Computer Science","Field-Programmable Logic and Applications"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/3-540-60294-1_107.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,3,21]],"date-time":"2025-03-21T22:58:55Z","timestamp":1742597935000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/3-540-60294-1_107"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1995]]},"ISBN":["9783540602941","9783540447863"],"references-count":10,"URL":"https:\/\/doi.org\/10.1007\/3-540-60294-1_107","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[1995]]}}}