{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,6]],"date-time":"2025-06-06T10:25:53Z","timestamp":1749205553854},"publisher-location":"Berlin, Heidelberg","reference-count":8,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540602941"},{"type":"electronic","value":"9783540447863"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[1995]]},"DOI":"10.1007\/3-540-60294-1_132","type":"book-chapter","created":{"date-parts":[[2012,2,26]],"date-time":"2012-02-26T18:08:44Z","timestamp":1330279724000},"page":"380-388","source":"Crossref","is-referenced-by-count":5,"title":["Reconfigurable logic for fault tolerance"],"prefix":"10.1007","author":[{"given":"Rajani","family":"Cuddapah","sequence":"first","affiliation":[]},{"given":"Massimiliano","family":"Corba","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2005,6,2]]},"reference":[{"key":"40_CR1","unstructured":"Xilinx, The Programmable Logic Data Book, 1994."},{"key":"40_CR2","unstructured":"J. S. N., Jean, \u201dFault-tolerant Array Processors Using N-and-half-track switches, Conference Proc. on Application Specific Array Processors, pp. 426\u2013437, 1990."},{"issue":"No.4","key":"40_CR3","doi-asserted-by":"crossref","first-page":"480","DOI":"10.1109\/12.54841","volume":"39","author":"V.P. Roychowdhury","year":"1990","unstructured":"V.P. Roychowdhury, J. Bruck, and T. Kailath, \u201dEfficient Algorithms for Reconfiguration in VLSI\/WSI Arrays\u201d, IEEE Trans. on Computers, Vol 39, No. 4, pp. 480\u2013488, April 1990.","journal-title":"IEEE Trans. on Computers"},{"key":"40_CR4","unstructured":"S. Kuo, W. Fuchs, \u201dSpare Allocation and Reconfiguration in Large Area VLSI\u201d, Conference Proc. 25th ACM\/IEEE Design Automation Conference, pp. 608\u2013612, 1988."},{"key":"40_CR5","doi-asserted-by":"crossref","unstructured":"K. Sugihara, T. Kikuno, \u201dOn Fault Tolerance of Reconfigurable Arrays Using Spare Processors\u201d, Conference Proc. Pacific Rim International Symposium on Fault Tolerant Systems, pp. 10\u201315, September 26\u201327, 1991.","DOI":"10.1109\/RFTS.1991.212972"},{"issue":"No.3","key":"40_CR6","doi-asserted-by":"crossref","first-page":"277","DOI":"10.1109\/4.75006","volume":"26","author":"J. Rose","year":"1991","unstructured":"J. Rose, S. Brown, \u201dFlexibility of Interconnection Structures for Field-Programmable Gate Arrays\u201d, IEEE J. Solid State Circuits, Vol. 26, No. 3, pp. 277\u2013282, March 1991.","journal-title":"IEEE J. Solid State Circuits"},{"key":"40_CR7","unstructured":"Programmable Electronics Performance Corporation Benchmark Suite 1, Version 1.2, May 28, 1993."},{"issue":"No.5","key":"40_CR8","doi-asserted-by":"crossref","first-page":"620","DOI":"10.1109\/43.127623","volume":"11","author":"S. Brown","year":"1992","unstructured":"S. Brown, J. Rose, \u201dA Detailed Router for Field-Programmable Gate Arrays\u201d, IEEE Trans. on Computer Aided Design, Vol 11, No. 5, pp 620\u2013628, May 1992.","journal-title":"IEEE Trans. on Computer Aided Design"}],"container-title":["Lecture Notes in Computer Science","Field-Programmable Logic and Applications"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/3-540-60294-1_132.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,4,28]],"date-time":"2021-04-28T01:35:57Z","timestamp":1619573757000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/3-540-60294-1_132"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1995]]},"ISBN":["9783540602941","9783540447863"],"references-count":8,"URL":"https:\/\/doi.org\/10.1007\/3-540-60294-1_132","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[1995]]}}}