{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,29]],"date-time":"2026-03-29T16:30:12Z","timestamp":1774801812866,"version":"3.50.1"},"publisher-location":"Berlin, Heidelberg","reference-count":16,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"value":"9783540602941","type":"print"},{"value":"9783540447863","type":"electronic"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[1995]]},"DOI":"10.1007\/3-540-60294-1_95","type":"book-chapter","created":{"date-parts":[[2012,2,26]],"date-time":"2012-02-26T18:08:09Z","timestamp":1330279689000},"page":"21-35","source":"Crossref","is-referenced-by-count":30,"title":["Self-timed FPGA systems"],"prefix":"10.1007","author":[{"given":"Rob","family":"Payne","sequence":"first","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2005,6,2]]},"reference":[{"key":"3_CR1","unstructured":"C.L.Seitz. System Timing, chapter 7. Addison-Wesley, Mead and Conway Introduction to VLSI Systems edition, 1980."},{"issue":"6","key":"3_CR2","doi-asserted-by":"crossref","first-page":"720","DOI":"10.1145\/63526.63532","volume":"32","author":"I.E. Sutherland","year":"1989","unstructured":"I.E.Sutherland. Micropipelines. Communications of the ACM, 32(6):720\u201338, 1989.","journal-title":"Communications of the ACM"},{"key":"3_CR3","unstructured":"S.B.Furber, P.Day, J.D.Garside, N.C.Paver, and J.V.Woods. A Micropipelined ARM. In T.Yanagawa and P.A.Ivey, editors, Proceedings of VLSI 93, pages 5.4.1\u20135.4.10, September 1993."},{"key":"3_CR4","doi-asserted-by":"crossref","unstructured":"A.J.Martin, S.M.Burns, T.K.Lee, D.Borkovic, and P.J.Hazewindus. The Design of an Asynchronous Microprocessor. In C.LSeitz, editor, Advanced Research in VLSI: Proceedings of the Decennial Caltech Conference on VLSI, pages 351\u2013373. MIT Press, 1989.","DOI":"10.21236\/ADA447727"},{"key":"3_CR5","doi-asserted-by":"crossref","unstructured":"X.Ling and H.Amano. WASMII: a data driven computer on a virtual hardware. In FCCM93: Proceedings of IEEE Workshop on FPGAs for Custom Computing Machines, 1993.","DOI":"10.1109\/FPGA.1993.279481"},{"key":"3_CR6","doi-asserted-by":"crossref","unstructured":"P.Lysaght, J.Stockwood, J.Law, and D.Girma. Artificial Neural Network Implementation on a Fine-Grained FPGA. In 4th International Workshop on Field Programmable Logic and Applications, 1994.","DOI":"10.1007\/3-540-58419-6_126"},{"issue":"2","key":"3_CR7","doi-asserted-by":"crossref","first-page":"173","DOI":"10.1007\/BF01607880","volume":"6","author":"E. Brunvand","year":"1993","unstructured":"E.Brunvand. Using FPGAs to Implement Self-Timed Systems. Journal of VLSI Signal Processing, 6(2):173\u2013190, August 1993.","journal-title":"Journal of VLSI Signal Processing"},{"key":"3_CR8","doi-asserted-by":"crossref","unstructured":"E.Brunvand. Using FPGAs to Prototype a Self-Timed Computer. In Workshop on Field Programmable Logic and Applications, pages 192\u2013198, 1992.","DOI":"10.1007\/3-540-57091-8_44"},{"key":"3_CR9","unstructured":"J.Oldfield and C.Kappler. Implementing Self-timed Systems: Comparision of Configurable Logic Arrays with Full Custom Circuits. In FPGAs: International Workshop on Field Programmable Logic and Applications, chapter 6.3. Abingdon EE&CS Books, 1991."},{"key":"3_CR10","doi-asserted-by":"crossref","unstructured":"P.Shaw and G.Milne. A Highly Parallel FPGA-Based Machine and its Formal Verification. Technical Report HDV-28-93, U. of Strathclyde, 1993.","DOI":"10.1007\/3-540-57091-8_41"},{"key":"3_CR11","unstructured":"M.Gamble, B.Rahardjo, and R.D.Mcleod. Reconfigurable FPGA Micropipelines. Technical report, U. of Manitoba, 1994."},{"key":"3_CR12","unstructured":"K. Maheswaran and V. Akella. Hazard-free Implementation of the Self-Timed Cell set for the Xilinx 4000 Series FPGA. Technical report, U.C.Davis, 1994."},{"key":"3_CR13","doi-asserted-by":"crossref","unstructured":"A.J.Martin. The Limitations to Delay-Insensitivity in Asynchronous Circuits. In W.J.Dally, editor, Sixth MIT Conference on Advanced Research in VLSI, pages 263\u2013278. MIT Press, 1990.","DOI":"10.21236\/ADA447737"},{"key":"3_CR14","doi-asserted-by":"crossref","unstructured":"S.Hauck, G.Borriello, S.Burns, and C.Ebeling. MONTAGE: An FPGA for Synchronous and Asynchronous Circuits. In Workshop on Field Programmable Logic and Applications, 1992.","DOI":"10.1007\/3-540-57091-8_28"},{"key":"3_CR15","doi-asserted-by":"crossref","unstructured":"M.E.Dean, D.L.Dill, and M.Horowitz. Self-Timed Logic Using Current-Sensing Completion Detection (CSCD). In Proc. International Conf. Computer Design (ICCD), pages 187\u2013191. IEEE Computer Society Press, October 1991.","DOI":"10.1109\/ICCD.1991.139878"},{"issue":"9","key":"3_CR16","doi-asserted-by":"crossref","first-page":"1005","DOI":"10.1109\/12.2252","volume":"C-37","author":"F.U. Rosenberger","year":"1988","unstructured":"F.U.Rosenberger, C.E.Molnar, T.J.Chaney, and T.Fang. Q-Modules: Internally Clocked Delay-Insensitive Modules. IEEE Transactions on Computers, C-37(9):1005\u20131018, September 1988.","journal-title":"IEEE Transactions on Computers"}],"container-title":["Lecture Notes in Computer Science","Field-Programmable Logic and Applications"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/3-540-60294-1_95.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,11,17]],"date-time":"2020-11-17T20:57:34Z","timestamp":1605646654000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/3-540-60294-1_95"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1995]]},"ISBN":["9783540602941","9783540447863"],"references-count":16,"URL":"https:\/\/doi.org\/10.1007\/3-540-60294-1_95","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"value":"0302-9743","type":"print"},{"value":"1611-3349","type":"electronic"}],"subject":[],"published":{"date-parts":[[1995]]}}}