{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,21]],"date-time":"2025-03-21T23:40:19Z","timestamp":1742600419447,"version":"3.40.2"},"publisher-location":"Berlin, Heidelberg","reference-count":10,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540603856"},{"type":"electronic","value":"9783540455165"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[1995]]},"DOI":"10.1007\/3-540-60385-9_10","type":"book-chapter","created":{"date-parts":[[2012,2,26]],"date-time":"2012-02-26T18:23:49Z","timestamp":1330280629000},"page":"161-170","source":"Crossref","is-referenced-by-count":1,"title":["Transforming Boolean relations by symbolic encoding"],"prefix":"10.1007","author":[{"given":"Gianpiero","family":"Cabodi","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Stefano","family":"Quer","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Paolo","family":"Camurati","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2005,6,2]]},"reference":[{"key":"10_CR1","doi-asserted-by":"crossref","unstructured":"K.S. Brace, R.L. Rudell, R. Bryant: Efficient Implementation of a BDD Package. Proc. IEEE\/ACM DAC'90, June 1990, pp. 40\u201345","DOI":"10.1145\/123186.123222"},{"issue":"No.8","key":"10_CR2","doi-asserted-by":"crossref","first-page":"667","DOI":"10.1109\/TC.1986.1676819","volume":"C-35","author":"R.E. Bryant","year":"1986","unstructured":"R.E. Bryant: Graph-based algorithms for boolean function manipulation. IEEE Transactions on Computers, Vol. C-35, No. 8, August 1986, pp. 667\u2013691","journal-title":"IEEE Transactions on Computers"},{"key":"10_CR3","unstructured":"G. Cabodi, P. Camurati, S. Quer: Symbolic Exploration of Large Circuits with Enhanced Forward\/Backward Traversals. Proc. IEEE EURO-DAC'94, Grenoble (France), September 1994, pp. 22\u201327 best paper award"},{"key":"10_CR4","doi-asserted-by":"crossref","unstructured":"G. Cabodi, P. Camurati, S. Quer: Computing subsets of equivalence classes for large FSMs. Proc. IEEE EURO-DAC'95, September 1995","DOI":"10.1109\/EURDAC.1995.527419"},{"key":"10_CR5","doi-asserted-by":"crossref","first-page":"75","DOI":"10.1090\/dimacs\/003\/07","volume":"3","author":"O. Coudert","year":"1991","unstructured":"O. Coudert, J.C. Madre, C. Berthet: Verifying temporal properties of sequential machines without building their state diagrams. AMS\/DIMACS Series in Discrete Mathematics and Theoretical Computer Science, Vol. 3, 1991, pp. 75\u201384","journal-title":"AMS\/DIMACS Series in Discrete Mathematics and Theoretical Computer Science"},{"key":"10_CR6","unstructured":"G. De Micheli: Synthesis and optimization of digital circuits. McGraw-Hill, 1994"},{"key":"10_CR7","doi-asserted-by":"crossref","unstructured":"G.D. Hachtel, M. Hermida, A. Pardo, M. Poncino, F. Somenzi: Re-Encoding Sequential Circuits to Reduce Power Dissipation. Proc. IEEE ICCAD'94, November 1994, pp. 70\u201373","DOI":"10.1109\/ICCAD.1994.629746"},{"key":"10_CR8","doi-asserted-by":"crossref","unstructured":"B. Lin, H.J. Touati, A. Richard Newton: Don't Care Minimization of Multi-Level Sequential Logic Networks. Proc. IEEE ICCAD'90, November 1990, pp. 414\u2013417","DOI":"10.1109\/ICCAD.1990.129940"},{"key":"10_CR9","doi-asserted-by":"crossref","first-page":"293","DOI":"10.1090\/dimacs\/003\/20","volume":"3","author":"C. Pixley","year":"1991","unstructured":"C. Pixley: A computational theory and implementation of sequential hardware equivalence. AMS\/DIMACS Series in Discrete Mathematics and Theoretical Computer Science, Vol. 3, 1991, pp. 293\u2013320","journal-title":"AMS\/DIMACS Series in Discrete Mathematics and Theoretical Computer Science"},{"key":"10_CR10","unstructured":"S. Quer, G. Cabodi, P. Camurati, L. Lavagno, E.M. Sentovich, R.K. Brayton: Incremental FSM Re-encoding for Simplifying Verification by Symbolic Traversal. IEEE International Workshop on Logic Synthesis, May 1995"}],"container-title":["Lecture Notes in Computer Science","Correct Hardware Design and Verification Methods"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/3-540-60385-9_10.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,3,21]],"date-time":"2025-03-21T23:01:52Z","timestamp":1742598112000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/3-540-60385-9_10"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1995]]},"ISBN":["9783540603856","9783540455165"],"references-count":10,"URL":"https:\/\/doi.org\/10.1007\/3-540-60385-9_10","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[1995]]}}}