{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,6]],"date-time":"2024-09-06T23:17:02Z","timestamp":1725664622630},"publisher-location":"Berlin, Heidelberg","reference-count":12,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540616269"},{"type":"electronic","value":"9783540706335"}],"license":[{"start":{"date-parts":[[1996,1,1]],"date-time":"1996-01-01T00:00:00Z","timestamp":820454400000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[1996]]},"DOI":"10.1007\/3-540-61626-8_58","type":"book-chapter","created":{"date-parts":[[2012,2,26]],"date-time":"2012-02-26T17:06:02Z","timestamp":1330275962000},"page":"432-440","update-policy":"http:\/\/dx.doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":5,"title":["Compiler reduction of invalidation traffic in virtual shared memory systems"],"prefix":"10.1007","author":[{"given":"M. F. P.","family":"O'Boyle","sequence":"first","affiliation":[]},{"given":"R. W.","family":"Ford","sequence":"additional","affiliation":[]},{"given":"A. P.","family":"Nisbet","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2005,6,8]]},"reference":[{"key":"58_CR1","unstructured":"Bodin F., O'Boyle M.F.P. A Compiler Strategy for SVM, Third Workshop on Languages, Compilers and Runtime Systems for Scalable Computing, New York, May 1995."},{"issue":"6","key":"58_CR2","doi-asserted-by":"crossref","first-page":"39","DOI":"10.1109\/2.55499","volume":"23","author":"H. Cheong","year":"1990","unstructured":"Cheong H., Veidenbaum A.V., Compiler Directed Cache Management in Multiprocessors, IEEE Computer, 23(6):39\u201348, June 1990.","journal-title":"IEEE Computer"},{"key":"58_CR3","doi-asserted-by":"crossref","unstructured":"Cheong H., Life-Span Strategy \u2014 A Compiler-Based Approach to Cache Coherence, Proceedings of ICS, July 1992.","DOI":"10.1145\/143369.143402"},{"key":"58_CR4","doi-asserted-by":"crossref","unstructured":"Darnell E., Kennedy K., Cache Coherence Using Local Knowledge, Proceedings of Supercomputing 1993, pages 720\u2013729, Nov 1993.","DOI":"10.1145\/169627.169821"},{"key":"58_CR5","doi-asserted-by":"crossref","unstructured":"Ford R.W., Nisbet A.N., Bull J.M. User-level VSM Optimisation and its Application Proceedings of PARA95, Lyngby, Denmark, LNCS, 1995.","DOI":"10.1007\/3-540-60902-4_26"},{"issue":"4","key":"58_CR6","doi-asserted-by":"publisher","first-page":"300","DOI":"10.1145\/161541.161544","volume":"11","author":"M. Hill","year":"1993","unstructured":"Hill M., Larus J., Reinhardt S., Cooperative Shared Memory, ACM Trans. on Computer Systems 11(4): 300\u2013318, Nov 1993.","journal-title":"ACM Trans. on Computer Systems"},{"key":"58_CR7","doi-asserted-by":"crossref","unstructured":"Lebeck A.R., Wood D.A. Dynamic Self Invalidation: Reducing Coherence Overhead in Shared-Memory Multiprocessors, Proceedings of ISCA '95, 1995.","DOI":"10.1145\/223982.223995"},{"key":"58_CR8","unstructured":"Louri A. and Sung H., A Compiler Directed Cache Coherence Scheme with Fast and Parallel Explicit Invalidation, Proceedings of ICPP, August 1992."},{"key":"58_CR9","doi-asserted-by":"crossref","unstructured":"Mounes-Toussi F., Lilja D.J., Li Z. An Evaluation of a Compiler Optimization for Improving the Performance of a Coherence Directory, Proceedings of ICS '94, July 1994.","DOI":"10.1145\/181181.181281"},{"key":"58_CR10","doi-asserted-by":"crossref","unstructured":"Nisbet A.N., Ford R.W., Spinning on Coherency: A New VSM Optimisation for Write-Invalidate, Proceedings of HPCN Europe, April 1996.","DOI":"10.1007\/3-540-61142-8_628"},{"key":"58_CR11","doi-asserted-by":"crossref","unstructured":"O'Boyle M.F.P.,Ford R.W., Nisbet A.N., Compiler Reduction of Invalidation Traffic in Virtual Shared Memory Systems, CNC Tech. Rep. June 1996.","DOI":"10.1007\/3-540-61626-8_58"},{"key":"58_CR12","doi-asserted-by":"crossref","unstructured":"Skelton, C.J. et al., EDS a Parallel Computer System for Advanced Information Processing, Parallel Architectures and Languages Europe, PARLE 92, July 1992.","DOI":"10.1007\/3-540-55599-4_77"}],"container-title":["Lecture Notes in Computer Science","Euro-Par'96 Parallel Processing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/3-540-61626-8_58","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,12,31]],"date-time":"2021-12-31T05:51:19Z","timestamp":1640929879000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/3-540-61626-8_58"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1996]]},"ISBN":["9783540616269","9783540706335"],"references-count":12,"URL":"https:\/\/doi.org\/10.1007\/3-540-61626-8_58","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[1996]]},"assertion":[{"value":"8 June 2005","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}},{"value":"This content has been made available to all.","name":"free","label":"Free to read"}]}}