{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,22]],"date-time":"2025-03-22T04:20:22Z","timestamp":1742617222829,"version":"3.40.2"},"publisher-location":"Berlin, Heidelberg","reference-count":21,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540617303"},{"type":"electronic","value":"9783540706700"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[1996]]},"DOI":"10.1007\/3-540-61730-2_2","type":"book-chapter","created":{"date-parts":[[2012,2,26]],"date-time":"2012-02-26T22:15:23Z","timestamp":1330294523000},"page":"14-23","source":"Crossref","is-referenced-by-count":1,"title":["Performance-directed technology mapping for LUT-based FPGAs \u2014 What role do decomposition and covering play?"],"prefix":"10.1007","author":[{"given":"Christian","family":"Legl","sequence":"first","affiliation":[]},{"given":"Klaus","family":"Eckl","sequence":"additional","affiliation":[]},{"given":"Bernd","family":"Wurth","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2005,6,6]]},"reference":[{"key":"2_CR1","unstructured":"Xilinx Inc., San Jose, CA-95125, The Programmable Logic Data Book, 1994."},{"key":"2_CR2","doi-asserted-by":"crossref","unstructured":"R. J. Francis, J. Rose, and Z. Vranesic, \u201cTechnology mapping of lookup table-based FPGAs for performance,\u201d in IEEE\/ACM International Conference on Computer-Aided Design (ICCAD), pp. 568\u2013571, 1991","DOI":"10.1109\/ICCAD.1991.185334"},{"key":"2_CR3","doi-asserted-by":"crossref","unstructured":"K.-C. Chen, J. Cong, Y. Ding, A. B. Kahng, and P. Trajmar, \u201cDAG-Map: Graph-based FPGA technology mapping for delay optimization,\u201d IEEE Design & Test of Computers, pp. 7\u201320, Sept. 1992.","DOI":"10.1109\/54.156154"},{"key":"2_CR4","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1109\/43.273754","volume":"13","author":"J. Cong","year":"1994","unstructured":"J. Cong and Y. Ding, \u201cFlowmap: An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs,\u201d IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems CAD, vol. 13, pp. 1\u201312, Jan. 1994. in ACM\/IEEE Design Automation Conference (DAC), pp. 213\u2013218, 1993.","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems CAD"},{"key":"2_CR5","doi-asserted-by":"crossref","unstructured":"J. Cong and Y.-Y. Hwang, \u201cSimultaneous depth and area minimization in LUT-based FPGA mapping,\u201d in ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays, pp. 68\u201374, Feb. 1995.","DOI":"10.1109\/FPGA.1995.241947"},{"key":"2_CR6","doi-asserted-by":"crossref","unstructured":"J. Cong and Y. Ding, \u201cOn nominal delay minimization in LUT-based FPGA technology mapping,\u201d in ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays, pp. 82\u201388, Feb. 1995.","DOI":"10.1109\/FPGA.1995.242045"},{"key":"2_CR7","unstructured":"H. Yang and D. F. Wong, \u201cEdge-Map: Optimal performance driven technology mapping for iterative LUT based FPGA designs,\u201d in IEEE\/ACM International Conference on Computer-Aided Design (ICCAD), pp. 150\u2013155, 1994."},{"key":"2_CR8","doi-asserted-by":"crossref","unstructured":"R. Murgai, N. Shenoy, R. K. Brayton, and A. Sangiovanni-Vincentelli, \u201cPerformance directed synthesis for table look up programmable gate arrays,\u201d in IEEE\/ACM International Conference on Computer-Aided Design (ICCAD), pp. 572\u2013575, 1991.","DOI":"10.1109\/ICCAD.1991.185335"},{"key":"2_CR9","doi-asserted-by":"crossref","unstructured":"P. Sawkar and D. Thomas, \u201cPerformance directed technology mapping for look-up table based FPGAs,\u201d in ACM\/IEEE Design Automation Conference (DAC), pp. 208\u2013212, 1993.","DOI":"10.1145\/157485.164672"},{"key":"2_CR10","doi-asserted-by":"crossref","unstructured":"J. Cong and Y. Ding, \u201cBeyond the combinatorial limit in depth minimization for LUT-based FPGA designs,\u201d in IEEE\/ACM International Conference on Computer-Aided Design (ICCAD), pp. 110\u2013114, Nov. 1993.","DOI":"10.1109\/ICCAD.1993.580040"},{"key":"2_CR11","doi-asserted-by":"crossref","unstructured":"J. Cong and Y.-Y. Hwang, \u201cStructural gate decomposition for depth-optimal technology mapping in LUT-based FPGA design,\u201d in ACM\/IEEE Design Automation Conference (DAC), pp. 726\u2013729, June 1996.","DOI":"10.1145\/240518.240656"},{"key":"2_CR12","doi-asserted-by":"crossref","unstructured":"E. M. Sentovich, K. J. Singh, C. Moon, H. Savoj, R. K. Brayton, and A. Sangiovanni-Vincentelli, \u201cSequential circuit design using synthesis and optimization,\u201d in IEEE International Conference on Computer Design (ICCD), pp. 328\u2013333, Oct. 1992.","DOI":"10.1109\/ICCD.1992.276282"},{"key":"2_CR13","doi-asserted-by":"crossref","unstructured":"C. Legl, B. Wurth, and K. Eckl, \u201cA Boolean approach to performance-directed technology mapping for LUT-based FPGA designs,\u201d in ACM\/IEEE Design Automation Conference (DAC), pp. 730\u2013733, June 1996.","DOI":"10.1145\/240518.240657"},{"key":"2_CR14","doi-asserted-by":"crossref","first-page":"484","DOI":"10.1145\/321088.321091","volume":"8","author":"H. A. Curtis","year":"1961","unstructured":"H. A. Curtis, \u201cA generalized tree circuit,\u201d Journal of the ACM, vol. 8, pp. 484\u2013496, 1961.","journal-title":"Journal of the ACM"},{"key":"2_CR15","doi-asserted-by":"crossref","unstructured":"J. P. Roth and R. M. Karp, \u201cMinimization over boolean graphs,\u201d IBM Journal of Research and Development, pp. 227\u2013238, 1962.","DOI":"10.1147\/rd.62.0227"},{"key":"2_CR16","doi-asserted-by":"crossref","unstructured":"B. Wurth, K. Eckl, and K. Antreich, \u201cFunctional multiple-output decomposition: Theory and an implicit algorithm,\u201d in ACM\/IEEE Design Automation Conference (DAC), pp. 54\u201359, June 1995.","DOI":"10.1145\/217474.217506"},{"key":"2_CR17","doi-asserted-by":"crossref","unstructured":"C. Legl, B. Wurth, and K. Eckl, \u201cAn implicit algorithm for support minimization during functional decomposition,\u201d in European Design and Test Conference (ED&TC), pp. 412\u2013417, March 1996.","DOI":"10.1109\/EDTC.1996.494334"},{"key":"2_CR18","doi-asserted-by":"crossref","unstructured":"H. J. Touati, H. Savoj, and R. K. Brayton, \u201cDelay optimization of combinational logic circuits by clustering and partial collapsing,\u201d in IEEE\/ACM International Conference on Computer-Aided Design (ICCAD), pp. 188\u2013191, 1991.","DOI":"10.1109\/ICCAD.1991.185227"},{"key":"2_CR19","doi-asserted-by":"crossref","first-page":"1062","DOI":"10.1109\/TCAD.1987.1270347","volume":"6","author":"R. K. Brayton","year":"1987","unstructured":"R. K. Brayton, R. Rudell, A. Sangiovanni-Vincentelli, and A. R. Wang, \u201cMIS: A multiple-level logic optimization of combinational logic,\u201d in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems CAD, vol. 6, pp. 1062\u20131081, Nov. 1987.","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems CAD"},{"key":"2_CR20","doi-asserted-by":"crossref","unstructured":"K. J. Singh, A. R. Wang, R. K. Brayton, and A. Sangiovanni-Vincentelli, \u201cTiming optimization of combinational logic,\u201d in IEEE\/ACM International Conference on Computer-Aided Design (ICCAD), pp. 282\u2013285, 1988.","DOI":"10.1109\/ICCAD.1988.122511"},{"key":"2_CR21","doi-asserted-by":"crossref","first-page":"1319","DOI":"10.1109\/43.329262","volume":"13","author":"A. H. Farrahi","year":"1994","unstructured":"A. H. Farrahi and M. Sarrafzadeh, \u201cComplexity of the lookup-table minimization problem for FPGA technology mapping,\u201d IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems CAD, vol. 13, pp. 1319\u20131332, Nov. 1994.","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems CAD"}],"container-title":["Lecture Notes in Computer Science","Field-Programmable Logic Smart Applications, New Paradigms and Compilers"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/3-540-61730-2_2.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,3,21]],"date-time":"2025-03-21T23:24:26Z","timestamp":1742599466000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/3-540-61730-2_2"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1996]]},"ISBN":["9783540617303","9783540706700"],"references-count":21,"URL":"https:\/\/doi.org\/10.1007\/3-540-61730-2_2","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[1996]]}}}