{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,26]],"date-time":"2025-09-26T13:38:15Z","timestamp":1758893895982},"publisher-location":"Berlin, Heidelberg","reference-count":8,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540617303"},{"type":"electronic","value":"9783540706700"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[1996]]},"DOI":"10.1007\/3-540-61730-2_35","type":"book-chapter","created":{"date-parts":[[2012,2,26]],"date-time":"2012-02-26T22:15:45Z","timestamp":1330294545000},"page":"327-336","source":"Crossref","is-referenced-by-count":58,"title":["A virtual hardware operating system for the Xilinx XC6200"],"prefix":"10.1007","author":[{"given":"Gordon","family":"Brebner","sequence":"first","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2005,6,6]]},"reference":[{"key":"35_CR1","unstructured":"Brebner: \u201cThe SPODE circuit design library for the XC6200,\u201d Internal report, Department of Computer Science, University of Edinburgh, 1996."},{"key":"35_CR2","doi-asserted-by":"crossref","unstructured":"Brebner and Gray: \u201cUse of reconfigurability in variable-length code detection at video rates,\u201d Proc. 5th International Workshop on Field Programmable Logic and Applications, Springer-Verlag 1995.","DOI":"10.1007\/3-540-60294-1_137"},{"key":"35_CR3","unstructured":"Eldredge and Hutchings: \u201cRRANN: a hardware implementation of the backpropagation algorithm using reconfigurable FPGAs,\u201d Proc. IEEE International Conference on Neural Networks, 1994."},{"key":"35_CR4","unstructured":"Hadley and Hutchings: \u201cDesign methodologies for partially reconfigured systems,\u201d Proc. IEEE Workshop on FPGAs for Custom Computing Machines, 1995."},{"key":"35_CR5","doi-asserted-by":"crossref","unstructured":"Kean, Churcher and Wilkie: \u201cXC6200 fastmap processor interface,\u201d Proc. 5th International Workshop on Field Programmable Logic and Applications, 1995.","DOI":"10.1007\/3-540-60294-1_96"},{"key":"35_CR6","unstructured":"Kwok: \u201cAn investigation of virtual hardware using FPGA technology,\u201d Honours year dissertation, Department of Computer Science, University of Edinburgh, 1996."},{"key":"35_CR7","doi-asserted-by":"crossref","unstructured":"Lysaght, Stockwood, Law and Girma: \u201cArtificial neural network implementation on a fine-grained FPGA,\u201d Proc. 4th International Workshop on Field Programmable Logic and Applications, 1994.","DOI":"10.1007\/3-540-58419-6_126"},{"key":"35_CR8","doi-asserted-by":"crossref","unstructured":"Wirthlin and Hutchings: \u201cImplementation approaches for run-time reconfiguration,\u201d Proc. 5th International Workshop on Field Programmable Logic and Applications, 1995.","DOI":"10.1007\/3-540-60294-1_136"}],"container-title":["Lecture Notes in Computer Science","Field-Programmable Logic Smart Applications, New Paradigms and Compilers"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/3-540-61730-2_35.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,11,17]],"date-time":"2020-11-17T21:09:44Z","timestamp":1605647384000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/3-540-61730-2_35"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1996]]},"ISBN":["9783540617303","9783540706700"],"references-count":8,"URL":"https:\/\/doi.org\/10.1007\/3-540-61730-2_35","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[1996]]}}}