{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T15:44:49Z","timestamp":1725551089416},"publisher-location":"Berlin, Heidelberg","reference-count":10,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540634652"},{"type":"electronic","value":"9783540695578"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[1997]]},"DOI":"10.1007\/3-540-63465-7_232","type":"book-chapter","created":{"date-parts":[[2010,4,5]],"date-time":"2010-04-05T15:22:48Z","timestamp":1270480968000},"page":"274-283","source":"Crossref","is-referenced-by-count":3,"title":["An hardware\/software partitioning algorithm for custom computing machines"],"prefix":"10.1007","author":[{"given":"Anton","family":"Velinov Chichkov","sequence":"first","affiliation":[]},{"given":"Carlos","family":"Beltr\u00e1n Almeida","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2005,7,29]]},"reference":[{"key":"28_CR1","doi-asserted-by":"crossref","unstructured":"P. Athanas and H.Silverman, \u201cProcessor reconfiguration trough instructionset metamorphosis: architecture and compiler\u201d, Computer, vol. 28, no. 3,pp. 11\u201318, March 1993.","DOI":"10.1109\/2.204677"},{"key":"28_CR2","unstructured":"Alfred V. Aho, Ravi Sethi and Jefferey D. Ullman, \u201cCompilers: Principles, Techniques and Tools\u201d, Addison Wesley, 1986."},{"key":"28_CR3","unstructured":"Peter M. Athanas, \u201cAn Adaptive Machine Architecture and Compiler for Dynamic Processor Reconfiguration\u201d, Technical Report LEMS-101, Brown University, February, 1992."},{"key":"28_CR4","doi-asserted-by":"crossref","unstructured":"Rolf Ernst Jorg Henkel Thomas Benner, \u201cHardware-Software Co-synthesis for Microcontrollers\u201d, IEEE Design & Test of Computers, December 1993, page 64.","DOI":"10.1109\/54.245964"},{"key":"28_CR5","unstructured":"Rajesh Kumar Gupta, \u201cCo-Synthesis of Hardware and Software for Digital Embedded Systems\u201d, Ph.D. dissertation Stanford University, December 10, 1993."},{"key":"28_CR6","unstructured":"D. D. Gajski, Frank Vahid Sanjiv Narayan Jie \u201cSpecification and design of embedded systems\u201d, Gong University of California at Irvine. PTR Prentice Hall 1994."},{"key":"28_CR7","unstructured":"Anton Chichkov, C. Beltr\u00e1n Almeida, \u201cIdentification and Optimisation of Parallelism in Hardware\/Software Partitioning\u201d, International Workshop on Logic and Architecture Synthesis, Grenoble France, December 1996."},{"key":"28_CR8","unstructured":"F. Kurdahi, Ms. Min Xu, \u201cArea & Timing Estimation Techniques for Lookup Table-Based FPGA with Application to High-Level Synthesis\u201d, International Workshop on Logic and Architecture Synthesis, Grenoble France, December 1996."},{"key":"28_CR9","unstructured":"John L. Hennessy, David A. Patterson, \u201cComputer Architecture a Quantitative Approach\u201d, Morgan Kaufmann Publishers, INC. San Mateo, California."},{"key":"28_CR10","unstructured":"Xilinx, \u201cThe Programmable Logic Data Book\u201d, 1993."}],"container-title":["Lecture Notes in Computer Science","Field-Programmable Logic and Applications"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/3-540-63465-7_232","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,5,27]],"date-time":"2019-05-27T20:17:10Z","timestamp":1558988230000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/3-540-63465-7_232"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1997]]},"ISBN":["9783540634652","9783540695578"],"references-count":10,"URL":"https:\/\/doi.org\/10.1007\/3-540-63465-7_232","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[1997]]}}}