{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,5]],"date-time":"2025-06-05T12:06:18Z","timestamp":1749125178632},"publisher-location":"Berlin, Heidelberg","reference-count":20,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540634652"},{"type":"electronic","value":"9783540695578"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[1997]]},"DOI":"10.1007\/3-540-63465-7_250","type":"book-chapter","created":{"date-parts":[[2010,4,5]],"date-time":"2010-04-05T15:22:48Z","timestamp":1270480968000},"page":"448-456","source":"Crossref","is-referenced-by-count":37,"title":["Satisfiability on reconfigurable hardware"],"prefix":"10.1007","author":[{"given":"Miron","family":"Abramovici","sequence":"first","affiliation":[]},{"given":"Daniel","family":"Saab","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2005,7,29]]},"reference":[{"key":"46_CR1","doi-asserted-by":"crossref","unstructured":"M. Abramovici, M. A. Breuer and A. D. Friedman, Digital Systems Testing and Testable Design, IEEE Press, 1994","DOI":"10.1109\/9780470544389"},{"key":"46_CR2","doi-asserted-by":"crossref","unstructured":"M. Abramovici and P. Menon, \u201cFault Simulation on Reconfigurable Hardware,\u201d Proc. IEEE Symp. on Field-Programmable Custom Computing Machines, April, 1997","DOI":"10.1109\/FPGA.1997.624618"},{"key":"46_CR3","doi-asserted-by":"crossref","unstructured":"J. Babb, M. Frank, and A. Agrawal, \u201cSolving graph problems with dynamic computation structures,\u201d in SPIE Photonics East: Reconfigurable Technology for Rapid Product Development & Computing, pp. 225\u2013236, November, 1996","DOI":"10.1117\/12.255820"},{"key":"46_CR4","doi-asserted-by":"crossref","unstructured":"R. Brayton, G. Hachtel, C. McMullen, and A. Sangiovanni-Vincentelli, Logic Minimization Algorithms for VLSI Synthesis, Kluwer Academic Publishers, 1984","DOI":"10.1007\/978-1-4613-2821-6"},{"key":"46_CR5","unstructured":"F. Brglez and H. Fujiwara, \u201cNeutral netlist of ten combinational benchmark circuits and a target translator in FORTRAN,\u201d Proc. IEEE Intn'l. Symp. on Circuits and Systems, June 1985."},{"issue":"3","key":"46_CR6","doi-asserted-by":"crossref","first-page":"54","DOI":"10.1109\/54.60606","volume":"7","author":"S. T. Chakradhar","year":"1990","unstructured":"S. T. Chakradhar, V. D. Agrawal, and M. L. Bushnell, \u201cNeural Net and Boolean Satisfiability Models of Logic Circuits,\u201d IEEE Design & Test of Computers, vol. 7, no. 3, pp. 54\u201357, October,1990","journal-title":"IEEE Design & Test of Computers"},{"key":"46_CR7","doi-asserted-by":"crossref","unstructured":"S. T. Chakradhar and V D. Agrawal, \u201cA Novel VLSI Solution to a Difficult Graph Problem,\u201d Proc. Intn.l. Symp. on VLSI Design, pp. 124\u2013129, January, 1990","DOI":"10.1109\/ISVD.1991.185104"},{"key":"46_CR8","doi-asserted-by":"crossref","unstructured":"S. A. Cook, \u201cThe Complexity of Theorem-Proving Procedures,\u201d Proc. 3rd Annual ACM Symp. on Theory of Computation, pp. 151\u2013158,1971","DOI":"10.1145\/800157.805047"},{"key":"46_CR9","doi-asserted-by":"crossref","unstructured":"S. Devadas, K. Keutzer, S. Malik, and A. Wang, \u201cCertified Timing Verification and the Transition Delay of a Logic Circuit,\u201d Proc. Design Automation Conf, pp. 549\u2013555, June, 1992","DOI":"10.1109\/DAC.1992.227744"},{"issue":"12","key":"46_CR10","doi-asserted-by":"crossref","first-page":"1137","DOI":"10.1109\/TC.1983.1676174","volume":"C-32","author":"H. Fujiwara","year":"1983","unstructured":"H. Fujiwara and T. Shimono, \u201cOn the Acceleration of Test Generation Algorithms,\u201d IEEE Trans. on Computers, vol. C-32, no 12, pp. 1137\u20131144, December, 1983.","journal-title":"IEEE Trans. on Computers"},{"issue":"3","key":"46_CR11","doi-asserted-by":"crossref","first-page":"215","DOI":"10.1109\/TC.1981.1675757","volume":"C-30","author":"P Goel","year":"1981","unstructured":"P Goel, \u201cAn Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits,\u201d IEEE Trans. on Computers, Vol. C-30, No. 3, pp. 215\u2013222, March, 1981.","journal-title":"IEEE Trans. on Computers"},{"key":"46_CR12","doi-asserted-by":"crossref","unstructured":"F. Hirose, K. Takayama, and N. Kawato, \u201cA Method to Generate Tests for Combinational Logic Circuits Using an Ultrahigh-speed Logic Simulator,\u201d Proc. Intn'l. Test Conf., pp 102\u2013107, Oct. 1988","DOI":"10.1109\/TEST.1988.207786"},{"issue":"1","key":"46_CR13","doi-asserted-by":"crossref","first-page":"4","DOI":"10.1109\/43.108614","volume":"11","author":"T Larrabee","year":"1992","unstructured":"T Larrabee, \u201cTest Pattern Generation Using Boolean Satisfiability,\u201d IEEE Trans. on CAD, Vol. 11, No. 1, pp. 4\u201315, January, 1992","journal-title":"IEEE Trans. on CAD"},{"key":"46_CR14","doi-asserted-by":"crossref","unstructured":"P C. McGeer et al., \u201cTiming Analysis and Delay-Fault Test Generation Using Path Recursive Functions,\u201d Proc. Intn'l. Symp. on CAD, pp. 180\u2013183, November 1991","DOI":"10.1109\/ICCAD.1991.185225"},{"key":"46_CR15","unstructured":"RPM Emulation System Data Sheet, Quickturn Systems Inc., 1991"},{"issue":"9","key":"46_CR16","doi-asserted-by":"crossref","first-page":"1167","DOI":"10.1109\/43.536723","volume":"15","author":"E. R. Stephan","year":"1996","unstructured":"E. R. Stephan, R. K. Brayton, and A. Sangiovanni-Vincentelli, \u201cCombinational Test Generation Using Satisfiability,\u201d IEEE Trans. on CAD, vol. 15, no. 9, pp. 1167\u20131176, Sept. 1996.","journal-title":"IEEE Trans. on CAD"},{"key":"46_CR17","doi-asserted-by":"crossref","unstructured":"T. Suyama, M. Yokoo, and H. Sawada, \u201cSolving Satisfiability Problems on FPGAs,\u201c Proc. Intn'l. Workshop on Field-Programmable Logic and Applications, 1996","DOI":"10.1007\/3-540-61730-2_14"},{"issue":"3","key":"46_CR18","first-page":"285","volume":"27","author":"K. Takayama","year":"1991","unstructured":"K. Takayama, F. Hirose, and N. Kawato, \u201cA Test Generation System Using a Logic Simulation Engine,\u201d Fujitsu Sci. Tech. J., vol. 27, no 3, pp. 285\u2013289, Sept. 1991","journal-title":"Fujitsu Sci. Tech. J."},{"key":"46_CR19","doi-asserted-by":"crossref","unstructured":"R.G. Wood and R.A. Rutenbar, \u201cFPGA Routing and Routability Estimation Via Boolean Satisfiability\u201d, Proc. Intn'l. Symp. on FPGAs, February 1997","DOI":"10.1145\/258305.258322"},{"key":"46_CR20","unstructured":"Y. Wu and S. Adham, \u201cBIST Fault Diagnosis in Scan-Based VLSI Environments,\u201d Proc. Intn'l. Test Conf., pp. 48\u201357, October 1996"}],"container-title":["Lecture Notes in Computer Science","Field-Programmable Logic and Applications"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/3-540-63465-7_250","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,5,27]],"date-time":"2019-05-27T20:18:26Z","timestamp":1558988306000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/3-540-63465-7_250"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1997]]},"ISBN":["9783540634652","9783540695578"],"references-count":20,"URL":"https:\/\/doi.org\/10.1007\/3-540-63465-7_250","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[1997]]}}}